Abstract: An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.

Abstract: A synchronization apparatus for data synchronization and method for data synchronization is disclosed. One embodiment provides clock signals which are phase-shifted relative to one another are used for synchronizing data packets in a serial-to-parallel conversion device in a write path and equally for synchronizing data packets in a parallel-to-serial conversion device in a read path.

Abstract: A signal processing circuit includes a first circuit including a first clock signal generator with an output for a first clock signal and a second clock signal generator with an output for a second clock signal and an input for a comparison signal. The second clock signal is generated by the second clock signal generator based on the comparison signal. A second circuit includes a phase detector with a first input for the first clock signal, with a second input for the second clock signal and an output for the comparison signal indicating a relation between the phases of the first clock signal received at the first input and the second clock signal received at the second input.

Abstract: A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a multiplexer. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for shifting the FIFO output pointer based on data read from the FIFO cells. The multiplexer is for receiving the value of the FIFO output pointer from the output pointer counter. The multiplexer is also for receiving the multiplexing information for shifting the FIFO output pointer. The multiplexer is further for shifting the value of the FIFO output pointer based on the multiplexing information.

Abstract: A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter and a write training block. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for moving the FIFO output pointer based on data read from the FIFO cells.

Abstract: Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit output. Each delay element is an active circuit with a fixed transit time. The input of the first delay element of the first chain is connected to the circuit input and the output of each delay element of the first delay chain is selectively connectable to the input of the (n?i+1)th delay element of the second delay chain via a respectively associated switch of a first group of switches, wherein i=1 . . . n is the ordinal number of the delay elements of the first delay chain. The output of the last delay element of the second chain is connected as a circuit output.

Abstract: One embodiment of the invention relates to a circuit arrangement for regulating a latency that is defined as a whole number n of periods T of a reference clock of frequency fc and is intended to elapse, as of a data transmission command, before the data which are to be transmitted from a data source appear at the end of the data path that is to be passed through and contains a chain of transmission elements having fixed delay times. The frequency fc may be set in a range from 1/Tmax to 1/Tmin, where Tmin is at least equal to ?f/n and ?f is equal to the sum of the fixed delay times in the data path. The data path is subdivided into n successive sections, each of which contains, at its input, a clock-controlled sampling element for accepting the data to be transmitted and has a propagation time that is considerably shorter than Tmin. The propagation time ?n of the last section (Sn) is considerably greater than zero.

Abstract: One embodiment of the invention relates to a circuit arrangement for regulating a latency that is defined as a whole number n of periods T of a reference clock of frequency fc and is intended to elapse, as of a data transmission command, before the data which are to be transmitted from a data source appear at the end of the data path that is to be passed through and contains a chain of transmission elements having fixed delay times. The frequency fc may be set in a range from 1/Tmax to 1/Tmin, where Tmin is at least equal to ?f/n and ?f is equal to the sum of the fixed delay times in the data path. The data path is subdivided into n successive sections, each of which contains, at its input, a clock-controlled sampling element for accepting the data to be transmitted and has a propagation time that is considerably shorter than Tmin. The propagation time ?n of the last section (Sn) is considerably greater than zero.

Abstract: A device for generating memory-internal command signals from a memory operation command includes a command input for receiving a memory operation command for performing a memory operation in a memory system, a clock signal input for receiving an external clock signal, and an output for applying the memory-internal command signal to a command signal line of the memory system. In the device, the memory-internal command signal is generated at a time which depends on the memory-internal command signal and which is selectively settable and synchronous with a rising or synchronous with a falling edge of the external clock signal.

Abstract: A device for generating memory-internal command signals from a memory operation command is provided comprising a command input for receiving a memory operation command for performing a memory operation in a memory system, a clock signal input for receiving an external clock signal and an output for applying the memory-internal command signal to a command signal line of the memory system. The device further includes a command signal generating means which is implemented in order to generate the memory-internal command signal using the memory operation command at a time which depends on the memory-internal command signal and which is selectively settable synchronous with a rising or synchronous with a falling edge of the external clock signal.