Abstract: An endless electrophotographic member, such as a developer roller, which indicates an improved resistance to nip banding. The improvement to nip banding may be provided by the use of an organic salt within a roller surface region. The roller may provide, at a nip location, a resistive surface layer having an electrical resistance that avoids the development of nip banding and relatively dark regions on printed media.

Abstract: An endless electrophotographic member, such as a developer roller, which indicates an improved resistance to nip banding. The improvement to nip banding may be provided by the use of an organic salt within a roller surface region. The roller may provide, at a nip location, a resistive surface layer having an electrical resistance that avoids the development of nip banding and relatively dark regions on printed media.

Abstract: Address error detection including a method that receives write data and a write address, the write address corresponding to a location in a memory. Error correction code (ECC) bits are generated based on the received write data. The write data is transformed at a computer based on the write address and the write data, to produce transformed write data. The transforming is configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between either the write address or the read address and data read from the location. The transformed write data and the ECC bits are written to the location in memory.

Abstract: A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.

Abstract: A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit.

Abstract: A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The initialized unknown Boolean states are then fed to one or more simulated logic elements and the simulator simulates the handling of the unknown Boolean state by the simulated logic elements. Examples of simulated logic elements include gates and latches, such as flip-flops, inverters, and basic logic gates. The processing results in at least one negative unknown Boolean state. An example of when a negative unknown Boolean state would result would be when the unknown Boolean state is inverted by an inverter. The resulting negative unknown Boolean state is then fed to other simulated logic elements that generate further simulation results based on processing the negative unknown Boolean state.

Abstract: An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.

Abstract: We disclose a particle comprising a matrix coated thereon and having a positive charge, the particle being of a size to allow aggregation of primate or human stem cells attached thereto. The particle may comprise a substantially elongate, cylindrical or rod shaped particle having a longest dimension of between 50 ?m and 400 ?m, such as about 200 ?m. It may have a cross sectional dimension of between 20 ?m and 30 ?m. The particle may comprise a substantially compact or spherical shaped particle having a size of between about 20 ?m and about 120 ?m, for example about 65 ?m. We also disclose a method of propagating primate or human stem cells, the method comprising: providing first and second primate or human stem cells attached to first and second respective particles, allowing the first primate or human stem cell to contact the second primate or human stem cell to form an aggregate of cells and culturing the aggregate to propagate the primate or human stem cells for at least one passage.

Abstract: Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.

Abstract: An integrated security event management system (ISEMS) is disclosed and is based on service-oriented architecture (SOA) and includes one or more computers connected to one or more service-providing devices. At least one of the computers comprises one or more modules that are adapted to perform the following tasks: tasks to dynamically discover the service-providing devices and their services within a transit security domain in about real-time; tasks to acquire asynchronous state information notifications in about real-time from the discovered services; tasks to determine one or more Boolean outcomes from the asynchronous state information in about real-time via a configurable rules engine; and tasks to evaluate the one or more Boolean outcomes in about real-time via a configurable policy engine to determine state changes of one or more security policies.

Abstract: A tire, rim, and rim-mounted measurement device assembly includes a rim having a measurement device circumferential mounting surface; a tire mounted over the rim and having an inner liner region located radially inward from a crown region of the tire; one or more pairs of measurement devices mounted to the rim circumferential surface. Each measurement device has an operatively extending and retracting component attached to a respective attachment position on the inner liner region, and each of the measurement devices cooperatively measuring a designated type of deformation of the tire crown region within a rolling tire footprint.

Abstract: A method of testing an electronic tag includes: embedding the electronic tag within an elongate carrier strip composed of a material having material properties simulating an end product material within which the tag resides embedded during end product use; positioning the embedded tag substantially within the carrier strip at a mid-portion between opposite end portions of the strip; positioning the mid-portion of the strip and the embedded tag over at least one curved support surface; engaging the end portions of the strip; and positioning a reader in a position operative to receive information from the electronic tag during a testing transmission sequence; reciprocally moving the strip mid-portion in a forward direction and a reverse direction over the curved support surface; and rendering the reader operational to receive information transmitted from the electronic tag as the strip mid-portion reciprocally moves in the forward and reverse directions.