Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.

Abstract: A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.

Abstract: An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.

Abstract: A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possible. Certain descriptors are defined to be “barrier descriptors.” When the DMA device encounters a barrier descriptor, it ensures that all of the previous descriptors complete before the barrier descriptor completes. The DMA device further ensures that any interrupt generated by a barrier descriptor will not assert until the data move associated with the barrier descriptor completes. The DMA controller only permits interrupts to be generated by barrier descriptors. The barrier descriptor concept also allows software to embed mailbox completion messages into the scatter/gather linked list of descriptors.

Abstract: Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.

Abstract: A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit.

Abstract: A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.

Abstract: A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.

Abstract: A tire and wheel rim assembly includes a tire supporting rim having an outward facing mounting surface; a tire mounted to the rim positioning an internal tire cavity over the rim mounting surface; a passageway extending through the rim for communicating air pressure between the tire cavity and a side of the rim opposite the tire cavity; and means for controllably regulating the flow of air through the passageway. A connecting member such as a bolt may extend through the rim outside mounting surface to affix a tire pressure monitoring housing to the rim and the axial passageway through the rim may be an axial bore through the bolt. Regulation of air flow through the passageway may be effected by setting the diameter of the passageway sufficiently small; or incorporating a needle orifice in the passageway; or incorporating a porous insert body into the passageway. The insert body may be composed of sintered metal and may be fused to the internal sidewalls of the bolt.

Abstract: A system and method for handling e-mail attachments in a data processing system. A client receives at least one message in a message database stored in a system memory, wherein the at least one message includes at least one attached file. The client displays a main preview of the at least one message, wherein the main preview of the at least one message includes an indicia that represents the at least one attached file. The client expands the main preview of the at least one message into a first sub-preview and a second sub-preview, wherein the first sub-preview represents the at least one message, and wherein the second sub-preview represents the at least one attached file. The client selects the second sub-preview to perform a function on the at least one attached file independent of the at least one message. The client performs the function on the at least one attached file independent of the at least one message.

Abstract: In a method and apparatus associated with a bus controller, a set of mechanisms are selectively added to the bus controller, as well as to slave devices connected to the bus controller. A mechanism is also added to one or more master devices connected to the bus controller, in order to provide the master devices with a transaction ordering capability. The added mechanisms collectively achieve the objective of supporting connection of multiple slave devices to a common controller interface, and at the same time allowing pipelined operation of the slave devices. One embodiment of the invention is directed to a method for use with a bus and an associated bus controller, wherein the bus controller has respective master and slave interfaces for use in selectively interconnecting master devices and slave devices. The method comprises the steps of connecting one or more of the master devices to one of the master interfaces, and connecting each of a plurality of slave devices to the same one of the slave interfaces.

Abstract: A design structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization is disclosed. In one embodiment of the design structure, a method in a computer-aided design system includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.

Abstract: An improved method, device and data processing system are presented. In one embodiment, the method includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.

Abstract: A direct memory access (DMA) device is structured as a loosely coupled DMA engine (DE) and a bus engine (BE). The DE breaks the programmed data block moves into separate transactions, interprets the scatter/gather descriptors, and arbitrates among channels. The DE and BE use a combined read-write (RW) command that can be queued between the DE and the BE. The bus engine (BE) has two read queues and a write queue. The first read queue is for “new reads” and the second read queue is for “old reads,” which are reads that have been retried on the bus at least once. The BE gives absolute priority to new reads, and still avoids deadlock situations.

Abstract: A tire and wheel rim assembly includes a tire supporting rim having an outward facing mounting surface; a tire mounted to the rim positioning an internal tire cavity over the rim mounting surface; a passageway extending through the rim for communicating air pressure between the tire cavity and a side of the rim opposite the tire cavity; and means for controllably regulating the flow of air through the passageway. A connecting member such as a bolt may extend through the rim outside mounting surface to affix a tire pressure monitoring housing to the rim and the axial passageway through the rim may be an axial bore through the bolt. Regulation of air flow through the passageway may be effected by setting the diameter of the passageway sufficiently small; or incorporating a needle orifice in the passageway; or incorporating a porous insert body into the passageway. The insert body may be composed of sintered metal and may be fused to the internal sidewalls of the bolt.

Abstract: An apparatus for dividing a bundle of sheet material into smaller bundles includes a platform having a front and back on which the bundle is placed on an edge, a back wall against which the bundle is placed, a recess in the platform, a sliding member moveable from the front to the back of the recess along an axis and pivotable about the axis and having a portion which extends above the platform, and a finger protruding rearwardly from the sliding member offset from the axis and having a length equal to the thickness of the smaller bundles. The sliding member is moved backwards until the portion which extends above the platform abuts the bundle. It is then pivoted to lift the finger under a part of the bundle and a smaller bundle is lifted upwards from the bundle such that a user can then remove that smaller bundle.

Abstract: A chipper and apex subassembly 100 as an intermediate article of manufacture in a pneumatic tire has an apex strip 30 formed as a continuous elastomeric strip of unvulcanized material having a bottom base portion 31 and two opposing sides 33, 34 extending towards the narrow outer tip 32 and a chipper ply strip 40 reinforced with parallel cords oriented on a bias angle relative to the length of the strip cojoined to the apex 30 along the length of the strips and attached to one side of the unvulcanized apex strips on an outer surface. The chipper 40 is spaced from the bottom base portion 31 of the apex 30 and extends widthwise towards the narrow outer tip 32 to form a subassembly 100 of a chipper 40 and apex 30 as an intermediate article of manufacture. Additionally the subassembly 100 can be attached to bead core 12 to make a subassembly 200 as a further intermediate article of manufacture.

Abstract: A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.

Abstract: A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.