Abstract: A radio-frequency apparatus includes an integrated circuit. The integrated circuit includes receiver analog circuitry, receiver digital circuitry, a digital-to-analog converter, and a signal selector. The receiver analog circuitry receives radio-frequency signals, and provides a first digital signal. The receiver digital circuitry receives the first digital signal, and provides a second digital signal. The digital-to-analog converter converts the second digital signal into a first analog signal. The signal selector receives the second digital signal and the first analog signal, and selectively provides one of the second digital signal and the first analog signal as an output signal of the integrated circuit.

Abstract: A sampled amplitude read channel incorporated within a magnetic disk storage system for reading data recorded tracks on a magnetic medium, where the data comprises user data sectors recorded at varying data rates across a plurality of predefined zones and embedded servo data sectors recorded at the same data rate across the zones. The read channel comprises a timing recovery component for synchronous sampling of a read signal from a magnetic read head positioned over the magnetic medium, a gain control component for adjusting the amplitude of the read signal, and a DC offset component for canceling a DC offset in the read signal. These components are dynamically configured to operate according to whether the read channel is processing user data or embedded servo data.

Abstract: A radio-frequency receiver circuitry includes a down-converter circuitry, an analog-to-digital converter circuitry, and a DC offset reduction circuitry. The down-converter circuitry accepts a received radio-frequency signal and processes the radio-frequency signal to provide an in-phase down-converted signal and a quadrature down-converted signal to the analog-to-digital converter circuitry. The analog-to-digital converter circuitry converts the in-phase and quadrature down-converted signals to an in-phase digital output signal and a quadrature digital output signal, respectively. The DC offset reduction circuitry couples to the analog-to-digital converter circuitry, and tends to reduce a DC offset transmitted to the in-phase and quadrature digital output signals.

Abstract: A radio-frequency (RF) apparatus includes front-end circuitry. The front-end circuitry includes a filter circuitry and an impedance matching circuitry. The filter circuitry has a differential output that has an output impedance. The filter circuitry filters signals outside a signal band of interest. The impedance matching network has a differential input coupled to the output of the filter circuitry. The impedance matching network also has a differential output coupled to a signal processing circuitry. The signal processing circuitry has an input impedance. The impedance matching network matches the input impedance of the signal processing circuitry to the output impedance of the filter circuitry.

Abstract: A buffer circuitry buffers a radio-frequency (RF) signal. The buffer circuitry includes a complementary pair of switches and a power source. The a complementary pair of switches has an input terminal and output terminal. The input terminal of the complementary pair of switches responds to the RF signal. The output terminal of the complementary pair of switches couples to an output of the buffer circuitry. The power source includes a capacitor coupled to a current source. The power source couples to the complementary pair of switches. The power source supplies power to the complementary pair of switches in a manner that the buffer circuitry supplies a substantially constant power level at its output.

Abstract: A voltage-controlled oscillator (VCO) generates an output signal with adjustable frequency. The VCO circuitry includes a variable capacitor circuitry and a voltage-generator circuitry. In response to a plurality of control signals, the variable capacitor circuitry adjusts the frequency of an output signal of the VCO circuitry. The voltage-generator circuitry generates the plurality of control signals and provides them to the variable capacitor circuitry. The voltage level of each of the plurality of the control signals differs by an offset voltage from the voltage level of the remaining signals in the plurality of signals.

Abstract: A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) circuitry. The VCO circuitry generates a first signal that has a first frequency. A divider circuitry couples to the VCO circuitry and, in response to the first signal, the divider circuitry generates a second signal that has a second frequency. The frequency of the second signal equals the frequency of the first signal divided by a number.

Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

Abstract: A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) that generates an output signal. The frequency of the output signal of the VCO circuitry is adjustable in response to a first control signal and a second control signal. The transmitter path circuitry also includes a first feedback circuitry and a second feedback circuitry that are responsive to the output signal of the VCO circuitry. The first feedback circuitry provides the first control signal to the VCO circuitry. The first control signal coarsely adjusts the frequency of the output signal of the VCO circuitry to a desired frequency. The second feedback circuitry supplies the second control signal to the VCO circuitry. The second control signal fine tunes the frequency of the output signal of the voltage-controlled oscillator circuitry to the desired frequency.

Abstract: A low-noise current reference circuitry includes a voltage source, a current source, and a controller. The voltage source generates a reference voltage. The current source provides a low-noise output current in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the reference voltage and a voltage derived from the output current. A low-noise voltage reference circuitry includes a reference voltage source, a voltage source, and a controller. The reference voltage source generates a reference voltage. The voltage source provides a low-noise output voltage in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the output voltage and the reference voltage.

Abstract: A calibration circuitry includes an adjustable capacitor, a voltage generator, a reference voltage generator, and a controller. The reference voltage generator provides a reference voltage. The voltage generator provides a measurement voltage that depends on the capacitance of the adjustable capacitor. The capacitance of the adjustable capacitor varies in response to a control signal. The controller provides the control signal based on the relative values of the reference voltage and the measurement voltage.

Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry coupled together. The receiver analog circuitry receives an RF signal. The receiver analog circuitry processes the received RF signal and generates a digital signal that it provides to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal provided by a receiver analog circuitry with a digital intermediate frequency (IF) local oscillator signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal. The digital filter circuitry provides a notch at a frequency that corresponds to a residual DC offset of the receiver analog circuitry.

Abstract: Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract: A disc storage system servo code detector is disclosed that provides enhanced error correction capabilities during both tracking and seeking by increasing a minimum distance dmin between valid codewords and by increasing a minimum distance {circumflex over ( )}dmin from the signal space between adjacent codewords to the decision boundaries of all other valid codewords. The signal space with respect to the minimum distances is not a limiting aspect of the invention; however, in the preferred embodiment the codewords are selected to maximize the minimum distances in Euclidean space. Thus, the read signal is sampled and equalized according to a partial response spectrum, and maximum likelihood detection is employed to detect the servo codewords in Euclidean space. The code rate is selected according to certain design criteria such as the amount of error correction desired, the data density, and the cost and complexity of the encoder/decoder circuitry.

Abstract: A method and apparatus for calibrating the components of a Partial Response Read Channel (PRML) integrated circuit utilized in a magnetic storage device including a channel quality circuit, incorporated within the read channel IC, for automatically measuring the performance of each component as data is read by the channel. An error measurement for each component is generated as an indicator of the component's performance, such as a sample error generated by measuring the difference between the samples read by the channel and expected samples. The read channel components are programmed over a range of settings to determine the settings that generate the minimum error. By programming the components with settings corresponding to minimum error rates, the read channel is optimized.

Abstract: A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.

Abstract: A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated binary sequence from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a read head positioned over the disk storage medium. The read channel comprises a sampling device, such as an analog-to-digital converter (A/D), for sampling the analog read signal to generate the discrete time sample values and for sampling at least one other auxillary analog input signal, such as a servo control signal. In this manner, performance characteristics of the read channel can be measured, such as the driving current applied to the servo control voice coil motor (VCM), without requiring additional hardware.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.

Abstract: A disk storage system is disclosed wherein user data received from a host system is first encoded according to a first channel code having a high code rate, and then encoded according to an ECC code, such as a Reed-Solomon code, wherein the ECC redundancy symbols are encoded according to a second channel code having low error propagation. In the preferred embodiment, the first channel code is a RLL (d,k) code having a long k constraint which allows for longer block lengths (and higher code rates). During read back, a synchronous read channel samples the analog read signal a synchronously and interpolates the asynchronous sample values to generate sample values substantially synchronized to the baud rate. In contrast to conventional synchronous-sampling timing recovery, interpolated timing recovery can tolerate a longer RLL k constraint because it is less sensitive to noise in the read signal and not affected by process variations in fabrication.