Abstract: A sampled amplitude read channel incorporated within a magnetic disk storage system for reading data recorded in concentric tracks on a magnetic medium, where the data comprises user data sectors recorded at varying data rates across a plurality of predefined zones and embedded servo data sectors recorded at the same data rate across the zones. The sampled amplitude read channel comprises a timing recovery component for synchronous sampling of a read signal from a magnetic read head positioned over the magnetic medium, a gain control component for adjusting the amplitude of the read signal, and a DC offset component for cancelling a DC offset in the read signal. These components are dynamically configured to operate according to whether the read channel is processing user data or embedded servo data.

Abstract: This invention provides apparatus and a method to assist in calibrating a read channel in a magnetic data storage system. More particularly, the invention provides a read channel including a digital noise generator. During a calibration procedure, the digital noise generator injects an analog noise signal into the read channel, thereby increasing the read channel's bit-error rate, and consequently allowing rapid calibration of the read channel. The digital noise generator comprises a number of linear feedback shift registers that together generate a pseudo-random digital word sequence, and a digital-to-analog converter that converts the pseudo-random digital word sequence into the analog noise signal. The digital-to-analog converter comprises a plurality of one-bit digital-to-analog converters whose outputs are summed by an analog adder.

Abstract: In a computer disk storage system for recording binary data, a sampled amplitude read channel comprises a sampling device for asynchronously sampling pulses in an analog read signal from a read head positioned over a disk storage medium, interpolated timing recovery for generating synchronous sample values, and a sequence detector for detecting the binary data from the synchronous sample values. The sequence detector comprises a demodulator for detecting a preliminary binary sequence which may contain bit errors, a remodulator for remodulating to estimated sample values, a means for generating sample error values, an error pattern detector for detecting the bit errors, an error detection validator, and an error corrector for correcting the bit errors. The remodulator comprises a partial erasure circuit which compensates for the non-linear reduction in amplitude of a primary pulse caused by secondary pulses located near the primary pulse.

Abstract: A sampled amplitude read channel reads information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate, and the channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.).

Abstract: A measurement circuit is provided to obtain data for monitoring the quality of performance from a digital read channel. Elements of the digital read channel including a sequence detector are incorporated into an integrated circuit together with the measurement circuit. The measurement circuit relates digitized samples of readback data from a magnetic storage device to surrounding samples so that particular samples can be collected in accordance with their surroundings. The circuit includes a programmable time window which can be repeatedly opened for data collection. The circuit is designed to collect various types of data including the bit error rate, sample value, squared sample error, squared gain error, squared timing error, and the occurrences of sample error when it is outside an acceptable programmable threshold. The measurement circuit includes a signal generator for producing a test pattern that is first stored and then read to produce the digitized readback sample values.

Abstract: An improved timing recovery phase-locked loop in a partial response recording channel comprising a means for generating a frequency error and a means for generating a phase error represented by a timing gradient. The frequency error is not affected by a DC offset in the input reference signal and is less susciptible to noise due to an increase in sensitivity. A state machine for generating expected samples is used to generate the timing gradient, rather than estimated signal samples, which results in a shorter acquisition preamble. When tracking arbitrary user data, the timing gradient is smoothed to reduce variations in the gain of the loop.

Abstract: A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons.

Abstract: A sampled amplitude read channel reads data from a magnetic medium by detecting digital data from a sequence of discrete time sample values generated by sampling an analog read signal from a read head positioned over the magnetic medium. The digital data comprises a preamble field followed by a sync mark followed by a data field. Timing recovery in the read channel synchronizes to a phase and frequency of the preamble field and a sync detector detects the sync mark in order to frame operation of an RLL decoder for decoding the detected data field. To decrease the probability of early misdetection, the sync mark is chosen to have minimum correlation with shifted versions of the sync mark concatenated with the preamble field. To further increase the fault tolerance, the sync mark detector is enabled by timing recovery relative to the end of the preamble field.

Abstract: A method and apparatus for computing, in real time, the coefficients C.sub..tau. (n) of a time varying FIR filter according to an optimum singular value decomposition (SVD) algorithm. The coefficients of a plurality of FIR filters are represented by a M.times.N matrix A.sub.M.times.N, where M is the number of FIR filters and N is the number of coefficients in the impulse response of each FIR filter (i.e., the number of filter taps). The A.sub.M.times.N matrix is factored into F.sub.M.times.N and G.sub.N.times.N matrices, and a singular value decomposition of the A.sub.M.times.N matrix is computed as A.sub.M.times.N =U.sub.M.times.N .cndot.D.sub.N.times.N .cndot.V.sub.N.times.N, where U.sub.M.times.N is a M.times.N unitary matrix, D.sub.N.times.N is a N.times.N diagonal matrix {.sigma..sub.1, .sigma..sub.2, . . . , .sigma..sub.N }, .sigma..sub.i are the singular values of A.sub.M.times.N (and .sigma..sub.1 .gtoreq..sigma..sub.2 . . . .gtoreq..sigma..sub.N .gtoreq.0), and V.sub.N.times.N is a N.times.

Abstract: A sampled amplitude read channel for reading information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. The channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.).

Abstract: A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter provides the two programmable delays using only one delay line thereby reducing the size and cost of the circuit. Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput.

Abstract: In a synchronous read channel for magnetic recording, a timing recovery phase-locked loop (PLL) comprises a technique for smoothing a timing gradient .DELTA.t computed from estimated sample values and actual sample values. If an estimated sample value for computing the timing gradient is zero, then the timing gradient is increased, and if all of the estimated sample values for computing the timing gradient are zero, then the timing gradient is copied from its prior value. Smoothing the timing gradient reduces gain variations in the PLL and results in more effective timing recovery.

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract: A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

Abstract: Disclosed is a pulse detector that uses four samples of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of the signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.

Abstract: A mixed analog and digital gain control circuit for controlling the amplitude of an analog input signal. The circuit has a variable gain amplifier that receives the signal from a read/write recording head preamplifier. The output of the variable gain amplifier is connected through a multiplexer and equalizer to an analog to digital converter for converting the analog signal to digital sample values at controlled sampling times. A gain control circuit receives the digital values and the output of a pulse detector indicating when a pulse has occurred. A gain error detector within the gain control circuit determines the amount of error in the amplitude of each detected pulse, and this error amount is filtered and sent through a digital to analog converter and then through an exponentiating circuit. The output of the exponentiating circuit is connected to a gain control input of the variable gain amplifier.

Abstract: A Viterbi detector is modified to reduce its implementation complexity. A partial-response signal may be viewed as a sequence of expected samples generated from a finite-state-machine model. In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. In this invention, an ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module.