Abstract: A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a group 1 of word lines WL0 to WLi?1, a group 2 of word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk?1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread1, Vread2, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: An AND type flash memory is provided. The AND type flash memory includes a plurality of memory cells connected in parallel between a source line and a bit line. The memory cell includes a charge accumulation layer including a SiN layer serving as a gate insulating film. In case of programming, electrons tunneled from a channel FN are accumulated in the charge accumulation layer of the memory cell. In case of erasing, the electrons accumulated in the charge accumulation layer of the memory cell are released to the channel.

Abstract: A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.

Abstract: An N+ layer 21 connected to a source line SL at both ends of Si pillars 23a to 23d standing in a vertical direction; N+ layers 30a and 30b connected to a bit line BL1; N+ layers 30c and 30d connected to a bit line BL2; the Si pillars 23a to 23d connected to the N+ layer 21; gate insulating layers 27a to 27d surrounding the Si pillars 23a to 23d; first gate conductor layers 28a and 28b surrounding the gate insulating layers 27a t 27d and connected to plate lines PL1 and PL2; and second gate conductor layers 29a and 29b connected to word lines WL1 and WL2 are disposed on a substrate 1. The Si pillars 23a and 23c have sections partially overlap each other in perspective view of the sections along line X1-X1? and line X2-X2?, and the same applies to the Si pillars 23b and 23d.

Abstract: A normally-off field effect transistor device includes a gate electrode structure having a first insulating film, a charge-accumulation gate electrode, a second insulating film and a gate electrode deposited one by one on a semiconductor, and a first capacitor formed by capacitive coupling between the charge-accumulation gate electrode and a source electrode. A charge is accumulated on the charge-accumulation gate electrode by a first current flowing through the first capacitor. The gate electrode structure further includes a stacked film having a third insulating film and a first semiconductor layer provided between the source electrode and the charge-accumulation gate electrode, with at least part of the first current flowing through the stacked film.

Abstract: A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a drive control line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the drive control line of the memory cell connected to an unselected page.

Abstract: A memory device includes pages each constituted by memory cells, and a page write operation and a page erase operation are performed. First and second impurity layers and first and second gate conductor layers in each memory cell is connected to a source line, a bit line, a word line, and a driving control line. In a page read operation, page data is read. In the page write and read operations, a selected driving control line is lowered to zero volt at a first reset time, the driving control line is isolated from a driving circuit at a second reset time, thereby putting the driving control line in a zero-volt floating state, and a selected word line is set at zero volt at a third reset time, thereby putting the driving control line in a negative-voltage floating state by capacitive coupling between the word line and the driving control line.

Abstract: A memory device includes pages each constituted by memory cells, and a page write operation of retaining a group of positive holes, inside a channel semiconductor layer, generated by an impact ionization phenomenon by controlling voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell and a page erase operation of discharging the group of positive holes by controlling the voltages are performed. The first and second impurity layers and the first and second gate conductor layers of each memory cell is connected to a source line, a bit line connected to a sense amplifier circuit, a word line, and a driving control line respectively. In a page read operation, page data in a selected page is read to the bit lines. To the driving control line connected to a non-selected page, a voltage of zero volt or lower is applied.

Abstract: A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.

Abstract: A dynamic flash memory cell is formed by: stacking a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, and a third material layer on a first impurity layer on a P-layer substrate; making a first hole that extends through the insulating layers and the material layers formed on the P-layer substrate; forming a semiconductor pillar by filling the first hole; making a second hole and a third hole by removing the first material layer and the second material layer; forming a first gate insulating layer and a second gate insulating layer by oxidizing a surface layer of the semiconductor pillar exposed inside the second hole and inside the third hole; and forming a first gate conductor layer and a second gate conductor layer by filling the second hole and the third hole.

Abstract: A normally-off vertical nitride semiconductor transistor device with low threshold voltage variation includes a drift layer containing a nitride semiconductor, a channel region electrically connected to the drift layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. The gate insulating film includes at least a first insulating film located at the channel region side, a second insulating film located at the gate electrode side, and a third insulating film between the second insulating film and the gate electrode, wherein the second insulating film has charge traps with energy levels located inside the band gaps of both the first and third insulating films, and the threshold voltage is adjusted by charges accumulated in the charge traps. The threshold voltage is used to block flowing current by substantially eliminating conduction carriers of the channel region by voltage applied to the gate electrode.

Abstract: A memory device and method of fabricating the same are provided. The memory device includes a substrate, a stacked structure, a channel layer, and a charge storage structure. The stacked structure is located on the substrate and includes a plurality of insulating layers and a plurality of conductive layers stacked alternately, and the stacked structure has holes. The channel layer is located in the hole and includes a first part and a second part. The number of grain boundaries in the second part is less than the number of grain boundaries in the first part. The charge storage structure is located between the first part and the plurality of conductive layers, and the charge storage structure and the second part sandwich the first part therebetween.

Abstract: A NAND flash memory and manufacturing method thereof are provided. The NAND flash memory is capable of preventing a short circuit between gates extending along a vertical direction. The NAND flash memory includes a substrate; a plurality of channel stacks formed on the substrate and extending along an X direction; an interlayer dielectric formed between the channel stacks; a plurality of trenches formed apart from each other in the interlayer dielectric and arranged along a Y direction; an insulator stack including a charge storage layer formed to cover sidewalls of each of the trenches; and a plurality of conductive vertical gates elongating along the vertical direction in a space formed by the insulator stack in each of the trenches and extending along the Y direction.

Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

Abstract: A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.

Abstract: A nitride semiconductor transistor device is disclosed. The device includes a first nitride semiconductor layer disposed over a substrate, and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor disposed over the first nitride semiconductor layer. Over the second nitride semiconductor layer, a first insulating film, a charge-storing gate electrode, a second insulating film, and a second gate electrode are formed in order thereon. A source electrode and a drain electrode are disposed over the second nitride semiconductor layer interposing the charge-storing gate electrode in a plane direction. The device further includes a first gate electrode capacitively coupling with the charge-storing gate electrode with an insulating film therebetween forming a first capacitor, and the charge-storing gate electrode is charged by an electron injection from the first gate electrode through the first capacitor.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a group 1 of word lines WL0 to WLi?1, a group 2 of word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk?1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread1, Vread2, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.