Abstract: A programming method of an NAND flash memory is provided, for narrowing a distribution width of a threshold voltage. The method includes a step of verification reading for verifying a threshold voltage of a selected memory cell after a programming voltage is applied to a selected word line. The verification reading further includes a step of pre-charging a voltage to a bit line, a step of discharging the pre-charged bit line to a source line, and a step of reading the voltage of the bit line after the discharging step. Regarding the discharge period from starting the discharging of the bit line to starting the read out, the discharge period of the verification reading after the initial programming voltage is applied is set longer than the discharge period of the verification reading after the subsequent programming voltage is applied.

Abstract: A programming method of an NAND flash memory is provided, for narrowing a distribution width of a threshold voltage. The method includes a step of verification reading for verifying a threshold voltage of a selected memory cell after a programming voltage is applied to a selected word line. The verification reading further includes a step of pre-charging a voltage to a bit line, a step of discharging the pre-charged bit line to a source line, and a step of reading the voltage of the bit line after the discharging step. Regarding the discharge period from starting the discharging of the bit line to starting the read out, the discharge period of the verification reading after the initial programming voltage is applied is set longer than the discharge period of the verification reading after the subsequent programming voltage is applied.

Abstract: A non-volatile semiconductor memory apparatus and a data erasing method thereof are provided to suppress deterioration in reliability due to data rewriting. An erasing method of a flash memory is provided, which includes the following steps. A control gate is maintained at 0V, a high-voltage erase pulse is applied to a P well, such that electrons is emitted from a floating gate to the P well. Then, the control gate is again maintained, and a weak erase pulse with a voltage lower than the erase pulse is applied to the P well.

Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

Abstract: A programming method for suppressing deterioration of an insulating layer in a memory cell is provided. In the programming method for a flash memory of the invention, a cell unit including programming units that have been programmed is electrically isolated from a bit line; a cell unit not including programming units is electrically coupled with the bit line; a programming voltage is applied to selected word lines; and a pass voltage is applied to non-selected word lines. Moreover, during a period of applying the programming voltage, carriers are generated in a P-well, and hot carriers passing through a depletion region and accelerated by an electric field are injected into the memory cell.

Abstract: A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract: A non-volatile semiconductor memory device includes a non-volatile memory cell array and a control circuit for controlling writing-in to the memory cell array. In the stage before an erasing pulse adding in an erasing process where data of written-in memory cells is erased, the control circuit detects a programming speed when writing-in to the memory cell array, determines a programming start voltage corresponding to the programming speed for every block or every word line, stores the determined programming start voltage in the memory cell array and reads-out the programming start voltage from the memory cell array to write-in predetermined data.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract: A programming method for suppressing deterioration of an insulating layer in a memory cell is provided. In the programming method for a flash memory of the invention, a cell unit including programming units that have been programmed is electrically isolated from a bit line; a cell unit not including programming units is electrically coupled with the bit line; a programming voltage is applied to selected word lines; and a pass voltage is applied to non-selected word lines. Moreover, during a period of applying the programming voltage, carriers are generated in a P-well, and hot carriers passing through a depletion region and accelerated by an electric field are injected into the memory cell.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

Abstract: A data reading method for a rewritable non-volatile memory module, a memory controller using the method, and a memory storage apparatus using the method are provided. The method includes applying a bias for reading data to a target word line electrically connected to a target memory cell and applying a bias for selecting bit lines to a target bit line electrically connected to the target memory cell. The method also includes applying a first bias to at least one word line adjacent to the target word line and applying a second bias to other word lines, and the first bias is lower than the second bias. The method further includes outputting a corresponding value according to a conduction state of a channel of the target memory cell. Accordingly, the method can effectively increase the gate controllability of the memory cell to prevent read errors.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract: A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.