Patents by Inventor Riichiro Shirota
Riichiro Shirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7952934Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.Type: GrantFiled: November 11, 2010Date of Patent: May 31, 2011Assignee: Powerflash Technology CorporationInventors: Riichiro Shirota, Ching-Hsiang Hsu, Cheng-Jye Liu
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Publication number: 20110108905Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Inventors: Masayuki ICHIGE, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Patent number: 7939406Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: May 5, 2009Date of Patent: May 10, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Publication number: 20110092033Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Inventors: Fumitaka Arai, Riichiro Shirota
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Publication number: 20110051526Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.Type: ApplicationFiled: November 11, 2010Publication date: March 3, 2011Inventors: Riichiro Shirota, Ching-Hsiang Hsu, Cheng-Jye Liu
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Patent number: 7888730Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: GrantFiled: March 19, 2007Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Patent number: 7884422Abstract: A semiconductor memory including a plurality of cell units arranged in a row direction, each of the cell units includes: a semiconductor region; a first buried insulating film provided on the semiconductor region; a second buried insulating film provided on the first buried insulating film, which has higher dielectric constant than the first buried insulating film; a semiconductor layer provided on the second buried insulating film; and a plurality of memory cell transistors arranged in a column direction, each of the memory cell transistors having a source region, a drain region and a channel region defined in the semiconductor layer.Type: GrantFiled: August 20, 2007Date of Patent: February 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Riichiro Shirota, Fumitaka Arai
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Patent number: 7875922Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region.Type: GrantFiled: December 20, 2007Date of Patent: January 25, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Fumitaka Arai, Riichiro Shirota
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Patent number: 7855918Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.Type: GrantFiled: June 24, 2008Date of Patent: December 21, 2010Assignee: Powerflash Technology CorporationInventors: Riichiro Shirota, Ching-Hsiang Hsu, Cheng-Jye Liu
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Publication number: 20100252875Abstract: A structure of a non-volatile memory is described, including a substrate, isolation structures disposed in and protrudent over the substrate, floating gates as conductive spacers on the sidewalls of the isolation structures protrudent over the substrate, and a tunneling layer between each floating gate and the substrate. A process for fabricating a non-volatile memory is also described. Isolation structures are formed in a substrate protrudent over the same, a tunneling layer is formed over the substrate, and then floating gates are formed as conductive spacers on the sidewalls of the first isolation structures protrudent over the substrate.Type: ApplicationFiled: April 3, 2009Publication date: October 7, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventor: Riichiro Shirota
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Publication number: 20100226173Abstract: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.Type: ApplicationFiled: May 17, 2010Publication date: September 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoharu Tanaka, Hiroshi Nakamura, Ken Takeuchi, Riichiro Shirota, Fumitaka Arai, Susumu Fujimura
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Patent number: 7791948Abstract: A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line.Type: GrantFiled: June 30, 2008Date of Patent: September 7, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Riichiro Shirota, Fumitaka Arai
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Patent number: 7755134Abstract: A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.Type: GrantFiled: June 20, 2007Date of Patent: July 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Nobutoshi Aoki, Masaru Kidoh, Ryota Katsumata, Masaki Kondo, Naoki Kusunoki, Toshiyuki Enda, Sanae Ito, Hiroyoshi Tanimoto, Hideaki Aochi, Akihiro Nitayama, Riichiro Shirota
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Patent number: 7746707Abstract: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.Type: GrantFiled: October 30, 2007Date of Patent: June 29, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Hiroshi Nakamura, Ken Takeuchi, Riichiro Shirota, Fumitaka Arai, Susumu Fujimura
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Publication number: 20100159657Abstract: A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Fumitaka ARAI, Riichiro Shirota, Makoto Mizukami
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Publication number: 20100149870Abstract: A non-volatile semiconductor memory and a writing method thereof are provided for preventing miswriting induced by gate-induced-drain leakage (GIDL). The non-volatile semiconductor memory comprises a non-volatile memory cell array 10 for recording multiple values by setting a plurality of different thresholds to each memory cell transistor that is connected in series between selection transistors Qs1 and Qs2 on two terminals of a selected bit line; and a control circuit 11 for controlling writing of the data from the memory cell array 10. The control circuit 11 records two values for at least a plurality of first memory cell transistors Q0, Q1, Q32 and Q33 respectively adjacent to the selection transistors Qs1 and Qs2 on two terminals of the bit line, and records more than three values for a plurality of second transistors Q2˜Q31 other than the first memory cell transistors.Type: ApplicationFiled: December 3, 2009Publication date: June 17, 2010Inventor: Riichiro SHIROTA
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Patent number: 7696559Abstract: A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.Type: GrantFiled: December 27, 2006Date of Patent: April 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Fumitaka Arai, Riichiro Shirota, Makoto Mizukami
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Patent number: 7616491Abstract: A bit line is shared by first and second NAND units. First and second selection transistors are connected in series between the bit line and the first NAND unit. Third and fourth selection transistors are connected in series between the bit line and the second NAND unit. A control unit changes a first and second signals and a potential of the bit line from a first level to a second level higher than a first level, and changes the potential of the bit line from the second level to the first level after changing the first signal from the second level to the first level.Type: GrantFiled: April 23, 2007Date of Patent: November 10, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Kamigaichi, Riichiro Shirota
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Publication number: 20090221128Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: May 5, 2009Publication date: September 3, 2009Inventors: Michiharu MATSUI, Seiichi MORI, Riichiro SHIROTA, Yuji TAKEUCHI, Takeshi KAMIGAICHI
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Patent number: 7573092Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: November 2, 2006Date of Patent: August 11, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi