Abstract: A photoresist is disclosed. The photoresist includes a polymer with one repeating unit and an absorbing unit.

Abstract: Integrated circuitry comprising an opaque material layer, such an interconnect metallization layer is first patterned with a maskless lithography to reveal an alignment feature, and is then patterned with masked lithography that aligns to the alignment feature. In some examples, the maskless lithography employs an I-line digital light processing (DLP) lithography system. In some examples the I-line DLP lithography system performs an alignment with IR illumination through a backside of a wafer. The maskless pattern may include dimensionally large windows within a frame around circuitry regions. A first etch of the opaque material layer may expose the alignment feature within the window, and a second etch of the opaque material may form IC features, such as interconnect metallization features.

Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.

Abstract: A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

Abstract: Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.

Abstract: A photoresist is disclosed. The photoresist includes a polymer with one repeating unit and an absorbing unit.

Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.

Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

Abstract: Reducing line edge roughness by particle beam exposure is generally described. In one example, a method includes forming one or more line structures on a surface of a semiconductor substrate, aligning the one or more line structures to a beam path of a particle beam such that particles of the particle beam travel within 45 degrees of parallel to a lengthwise direction of the one or more line structures, and exposing the one or more line structures to the particle beam to reduce line edge roughness of the one or more line structures wherein an incident angle of the particle beam to the surface of the semiconductor substrate is between about 45 degrees and about 90 degrees, where 0 degrees is normal to the surface of the semiconductor substrate.

Abstract: A light source chamber in an Extreme Ultraviolet (EUV) lithography system may include a secondary plasma to ionize debris particles created by the light source and a foil trap to trap the ionize particles to avoid contamination of the collector optics in the chamber.

Abstract: Passivation coatings and gettering agents may be used in an Extreme Ultraviolet (EUV) source which uses tin (Sn) vapor as a plasma “fuel” to prevent contamination and corresponding loss of reflectivity due to tin contamination. The passivation coating may be a material to which tin does not adhere, and may be placed on reflective surfaces in the source chamber. The gettering agent may be a material that reacts strongly with tin, and may be placed outside of the collector mirrors and/or on non-reflective surfaces. A passivation coating may also be provided on the insulator between the anode and cathode of the source electrodes to prevent shorting due to tin coating the insulator surface.

Abstract: In an implementation, energy reaching the lower surface of a photoresist may be redirected back into the photoresist material. This may be done by, for example, reflecting and/or fluorescing the energy from a hardmask provided on the wafer surface back into the photoresist.

Abstract: Erosion of material in an electrode in a plasma-produced extreme ultraviolet (EUV) light source may be reduced by treating the surface of the electrode. Grooves may be provided in the electrode surface to increase re-deposition of electrode material in the grooves. The electrode surface may be coated with a porous material to reduce erosion due to brittle destruction. The electrode surface may be coated with a pseudo-alloy to reduce erosion from surface waves caused by the plasma in molten material on the surface of the electrode.

Abstract: Electric fields may be advantageously used in various steps of photolithographic processes. For example, prior to the pre-exposure bake, photoresists that have been spun-on the wafer may be exposed to an electric field to orient aggregates or other components within the unexposed photoresist. By aligning these aggregates or other components with the electric field, line edge roughness may be reduced, for example in connection with 193 nanometer photoresist. Likewise, during exposure, electric fields may be applied through uniquely situated electrodes or using a radio frequency coil. In addition, electric fields may be applied at virtually any point in the photolithography process by depositing a conductive electrode, which is subsequently removed during development. Finally, electric fields may be applied during the developing process to improve line edge roughness.

Abstract: A magnetic and/or electric field may be generated around collector optics in an EUV lithography system to deflect debris particles from the reflective surfaces of the optics. The magnetic and/or electric field may be generated by a solenoid structure around the optics or by passing current through inner an outer shells in a nested shell arrangement.

Abstract: A reticle carrier for an Extreme Ultraviolet (EUV) reticle may include nested grids of electret fibers to provide active protection from contamination without a power supply. The reticle carrier may include in-line sensors for in-situ monitoring of contamination. Grids of electret fibers may also be used in an EUV pellicle.

Abstract: A reticle carrier for an Extreme Ultraviolet (EUV) reticle may include nested grids of electret fibers to provide active protection from contamination without a power supply. The reticle carrier may include in-line sensors for in-situ monitoring of contamination. Grids of electret fibers may also be used in an EUV pellicle.

Abstract: Electric fields may be advantageously used in various steps of photolithographic processes. For example, prior to the pre-exposure bake, photoresists that have been spun-on the wafer may be exposed to an electric field to orient aggregates or other components within the unexposed photoresist. By aligning these aggregates or other components with the electric field, line edge roughness may be reduced, for example in connection with 193 nanometer photoresist. Likewise, during exposure, electric fields may be applied through uniquely situated electrodes or using a radio frequency coil. In addition, electric fields may be applied at virtually any point in the photolithography process by depositing a conductive electrode, which is subsequently removed during development. Finally, electric fields may be applied during the developing process to improve line edge roughness.