Abstract: An electrostatic discharge protection clamp particularly useful for with bipolar and biCMOS integrated circuits include an NPN transistor formed in an isolated tub in an epitaxial layer grown on a substrate. The collector of the NPN transistor is connected to the input terminal, and the emitter of the NPN transistor is connected to the substrate. A resistor interconnects the base and the emitter. Advantageously, the P-doped base can abut the P-doped isolation region forming the tub, and the P-doped isolation region can interconnect the emitter to the substrate. Below BV.sub.CES the clamp will look like an open circuit, and above BV.sub.CES the transistor will start conducting current. The transistor will break down collector to base. Conduction of the transistor causes a voltage drop across the base-emitter junction, and when this voltage drop exceeds the base-emitter forward voltage the transistor will turn on.

Abstract: A reference voltage generator is presented for use in a differential amplifier. The reference voltage provided by the generator tracks the non-signal dc conditions of a differential input stage and provides a reference voltage to a level-shifting stage so that feedforward compensation can be used to provide extended bandwidth without settling time problems.

Abstract: A new level shifting circuit is presented which does not restrict the upper limit of the common-mode input range of an operational amplifier. This is important particularly in operational amplifiers designated to operate with low power supply voltages. Significant parameters. of the operational amplifier, such as the gain and the slew rate, can be controlled without adversely affecting the common-mode input voltage range. The level shifting stage operates nondifferentially to avoid stability problems found in differential stages. A further improvement is accomplished using current balancing to achieve gain enhancement.

Abstract: An operational amplifier having input and output stages with positive capacitive feedback to the output stage derived from a point in the circuit where the voltage is proportional to the output voltage.

Abstract: A constant current amplifier stage for a voltage comparator circuit includes a first CMOS transistor pair having a common gate terminal and a common drain terminal and a second CMOS transistor pair which functions as a load for the first CMOS transistor pair. The second CMOS transistor pair has a common gate terminal and a common drain terminal both of which are connected to the common drain terminal of the first CMOS transistor pair. The transistors are configured so that the current through the first transistor pair at null is at least twice the current through the second transistor pair at null voltage.

Abstract: The present disclosure is of a novel circuit for controlling the impedance of an integrated circuit node during power-off and transient power conditions. The circuit includes a PNP transistor having an emitter-collector circuit connected between the circuit node and a ground node. The base of the transistor is connected to the ground node by a resistance, which holds the voltage at the base of the PNP transistor near ground potential when a signal is applied to the circuit node. The resistance can be implemented with a pinch resistor or as a FET transistor. The emitter of the PNP transistor clamps the voltage at the node to a value equal to the voltage drop across the resistor plus the forward voltage drop across the emitter-base circuit of the PNP transistor, the sum of which is less than the minimally necessary base-emitter turn-on voltage of a Darlington-connected NPN transistor pair.

Abstract: A high speed BIFET junction field effect transistor is formed in an epitaxial layer of one conductivity type and includes source and drain regions of opposite conductivity type interconnected by a thin channel region of the opposite conductivity type. A thin surface layer of the one conductivity type is formed over the channel region, and a highly conductive contact is formed on the surface layer intermediate the source and drain regions. The surface contact can comprise highly doped polycrystalline silicon material with a metal layer on the surface thereof. The surface contact and the epitaxial layer underlying the channel region comprise gates for the field effect transistor. Increased speed of operation comes from the increased conductivity of the surface contact.

Abstract: Disclosed is a switched capacitor filter block having a nonlinear quality coefficient, Q, whereby quality can be enhanced while limiting the size of feedback resistors in the filter block. A pair of capacitors alternately switchably connect an input signal to the input of integrator whereby the sampling frequency is twice the switching frequency. The filter block is readily fabricated in a monolithic integrated circuit with the feedback resistors being thin-film resistors formed on the surface of the monolithic integrated circuit. Such a circuit configuration is more accurate in programming and requires only one mask step in fabrication to program.

Abstract: A high thermal resistance bonding material for semiconductor chips includes a binder such as epoxy or polyimide and high thermal resistance material dispersed therein such as glass micropheres, glass beads, ceramic microspheres and ceramic beads. The particles of high thermal resistance material are sieved to obtain particles of generally uniform size. In plastic-encapsulated semiconductor chips, each chip is enveloped by the bonding material.

Abstract: A non-linear temperature correction circuit is provided which utilizes, in one embodiment, a pair of semiconductor elements such as a pair of transistors electrically connected to a common biasing current having a negative temperature coefficient and a negative temperature coefficient voltage is applied between the bases of the transistors. The output of one of the transistors is a non-linear output current which is non-linear with respect to temperature and where the output current has an inflection point.

Abstract: A charge pump circuit is integrated form utilizes a dual emitter transistor switch having low saturation voltage. The low saturation voltage for the transistor is provided by deriving a base bias voltage from the doubled voltage (2V.sub.cc) and a collector voltage from the voltage supply (V.sub.cc). Current-limiting for the transistor is provided by connecting one emitter to the base bias circuitry whereby the second emitter acts as a collector when the transistor saturates, thereby limiting the base drive and causing current-limiting.

Abstract: A circuit is provided for distributing load current among multiple power transistors in an output stage, each power transistor being adapted to conduct current over a different range of collector-emitter voltages. The circuit includes a first power transistor having a large ballast resistance for conducting current between the input and output of the circuit when the input/output voltage differential is high, and a second power transistor having a small ballast resistance for conducting current between the input and output of the circuit when the input/output voltage differential is low. Both transistors respond to a single control signal, and buffering is provided to prevent either transistor from overloading the common control point. Individual current limit protection circuitry is provided for each transistor, including a foldback network which reduces the current limit value of the current limit circuitry when the input/output voltage differential reaches a threshold value.

Abstract: An arrangement for cancelling the input bias current, at picoampere levels, in linear integrated circuits such as operational amplifiers, comparators, and the like is disclosed herein. This arrangement utilizes circuitry including a tracking transistor which is virtually independent of the presence or absence of leakage current in the overall integrated circuit, even at relatively high temperatures, for example 125.degree. C., where leakage current can be most significant.

Abstract: A semiconductor device wherein surface stabilization is provided by a shallow layer of ion implanted doping material on the surface of the semiconductor and beneath the passivating oxide layer. One embodiment is a bipolar transistor including a collector region, a base region and an emitter region, the base region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a zener diode device with an anode region and a cathode region, the cathode region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a JFET with a gate region and a source and drain region and a channel region extending through the gate region between the source and drain regions, the channel region being provided with the shallow ion implanted layer at the surface thereof.

Abstract: A pair of transistors, connected as a differential amplifier, is operated so that the transistors run at different current densities. A voltage divider is coupled across a pair of circuit terminals so that a portion of the terminal voltage is coupled to and used to differentially bias the transistors. An amplifier, responsive to the transistors differential output, and coupled to the divider, is used to vary the terminal voltage to force the differential output to zero. The transistor bias voltage thus generated has a positive temperature coefficient of voltage. A forward biased diode, which has a negative temperature coefficient of voltage, is also incorporated into the divider. When the terminal voltage is made equal to the semiconductor bandgap, the two temperature sensitive terms cancel to compensate the reference voltage.

Abstract: Apparatus for interrupting power to a plurality of parallel loads such as lighting circuits and selectively reapplying power to the loads includes a first switch serially interconnecting the loads to a power line. Second switch circuits are serially connected with each load whereby interruption of power to a load for a predetermined period of time opens the switch circuits. The switch circuits include bidirectional conduction devices such as triacs which require a gating signal before becoming conductive. A resistor-capacitor circuit provides a gating signal to the triac to maintain conduction thereof for the predetermined period of time.

Abstract: A semiconductor device wherein surface stabilization is provided by a shallow layer of ion implanted doping material on the surface of the semiconductor and beneath the passivating oxide layer. One embodiment is a bipolar transistor including a collector region, a base region and an emitter region, the base region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a zener diode device with an anode region and a cathode region, the cathode region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a JFET with a gate region and a source and drain region and a channel region extending through the gate region between the source and drain regions, the channel region being provided with the shallow ion implanted layer at the surface thereof.

Abstract: A pair of common base connected transistors have their emitters coupled to provide the input terminals of a differential amplifier. The collectors are coupled to a current mirror that provides a small current bias that operates the transistors at equal current densities. The common bases are coupled to a node that is driven to a level that causes the bases to track the emitters with a one V.sub.BE offset that will therefore automatically adjust to conform to the applied current. When a remotely grounded transducer is coupled to the amplifier input it can operate at a common mode potential outside of the span of the power supply that operates the amplifier.

Abstract: A composite transistor suitable for use in monolithic integrated circuits is characterized as having extremely high current gain, stable operation and low leakage current. Two vertical NPN transistors are coupled into a circuit configuration, along with two lateral PNP transistors, that has three terminals. These terminals behave as a single NPN transistor having characteristics that are superior to those of a conventional NPN transistor.

Abstract: A voltage reducing circuit device for reducing the RMS value of an incoming AC voltage is disclosed herein. This device is especially suitable for reducing line voltage applied to a load requiring lower voltage. In a preferred embodiment, the device is one which allows a domestic made 115 VAC small heating apparatus, such as a hair dryer, to be used in foreign countries where the 230 VAC service is available. In any case, the device is one which is relatively insensitive to fluctuations in line voltage and to changes in frequency.