Abstract: A clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The circuitry receives a clock signal, a clock enable signal having either an enable value or a disable value, and a power mode signal having either a low power value (indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down), or a functional mode value (indicating the plurality of synchronous elements are to be powered). A clock gating unit has logic circuitry that is configured to output the clock signal or the predetermined gated value depending upon the low power value and the functional mode value.

Abstract: An integrated circuit 2 is formed of multiple wafer layers 4, 6, 8, 10 arranged in a stack and connected with through silicon vias 12. Mechanical strain sensors 26, 28, 30, 32 in the form of ring oscillators are provided proximal to the through silicon vias 12 and detect mechanical strain associated with the through silicon via 12. The measured mechanical strain may be used to dynamically adjust operating parameters of the integrated circuit either as a whole or in regions where the mechanical strain is detected. The operating parameters adjusted can include clock frequency, operating voltage and heat generation.

Abstract: A static random access memory (SRAM) includes a data line for transferring data to and from the memory and at least one reset line, a plurality of storage cells, each cell including an asymmetric feedback loop; an access device for selectively providing a connection between the at data line and the cell's first access node; a reset device for selectively providing a connection between a reset line and the cell's second access node. The SRAM further includes data access control circuitry for generating control signals for independently controlling the access device and the reset device and to generate a data access control signal. The SRAM also generates a reset control signal to trigger the reset device to provide the connection between the at least one reset line and the second access node in response to a write request to write the complementary predetermined value to the storage cell.

Abstract: A memory array comprises a plurality of rows and a plurality of columns, each row comprising at least one addressable word. The memory array comprises at least one redundant row and at least one redundant column. Error detection circuitry analyzes the memory array by addressing words and detecting errors within the addressed words. Error repair circuitry selects for a detected error either a redundant row or a redundant column to replace one of the row or column containing the error. It is determined for the detected error whether the error is a single error bit in the addressed word or whether it is one of a plurality of error bits within the word. If the error is the latter, then the error repair circuitry preferentially selects a redundant row rather than a redundant column to repair the error.

Abstract: A clock gating circuitry unit for supplying either a clock signal or a predetermined gated value to a plurality of synchronous elements within an integrated circuit is disclosed. The clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value.

Abstract: A method is provided for altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device. The method comprises identifying a subset of the memory cells whose value of the chosen characteristic is within a predetermined end region of the distribution, and then performing a burn-in process during which one or more operating parameters of the memory device are set to induce aging of the memory cells. During the burn-in process, for each memory cell in the subset, the value stored in that memory cell is fixed to a selected value which exposes that memory cell to a stress condition. In contrast, for each memory cell not in the subset, the value stored in that memory cell is alternated during the burn-in process in order to alleviate exposure of that memory cell to the stress condition. Such an approach allows a tightening of the distribution of the chosen characteristic, thus improving the worst case memory cells.

Abstract: A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access control circuits each for controlling a voltage level supplied to a corresponding one of the at least two access control lines in response to an access request, the at least two access control circuits each comprising a capacitor and switching circuitry; routing circuitry for routing the access request and a boost signal to a selected one of the at least two access control circuits in dependence upon an address associated with the access request; wherein the at least two access control circuits are each responsive to: receipt of the access request from the routing circuitry to connect the selected access control line to a supply voltage; and receipt of the boost signal from the routing circuitry to disconnect the supply voltage from the access con

Abstract: An integrated circuit and method for testing memory on the integrated circuit are provided. The integrated circuit has processing logic for performing data processing operations on data, and a plurality of memory units for storing data for access by the processing logic. Further, memory test logic is provided to perform a sequence of tests in order to seek to detect memory defects in the memory units. The memory test logic comprises a plurality of test wrapper units, each test wrapper unit associated with one of the memory units and being operable to execute tests on the associated memory unit, and a test controller for controlling performance of the sequence of tests by communicating with each of the test wrapper units to provide test data defining each test to be executed by that test wrapper unit.

Abstract: An integrated circuit is provided including at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory calls, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line.

Abstract: A multiport memory is provided with multiple data access paths A, B, each having a respective independent clock signal CLKA, CLKB. During self test operation a duplicate clock enable signal DPCLKTESTEN is used to enable one of these clock signals CLKA, CLKB to be used as a shared clock signal by all data access paths A, B. An external memory adjust signal EMAA. EMAB is used to adjust one of these shared clock signals to form a modified shared clock signal for at least one of the data paths being tested. In this way, worst-case scenarios can be more readily investigated comprising clocks with the same frequency but small differences in phase.

Abstract: A technique for characterising variation in a performance parameter(s) of circuit cells within a circuit cell library with perturbations in manufacturing process parameters uses a statistical approach whereby the statistical distribution of performance parameter(s) resulting from a joint distribution across manufacturing process parameter space is determined. The perturbation in manufacturing process parameter which results in a characteristic amount of variation is then identified and common sets of such perturbations used to group families of circuit cells together. Families of circuit cells have a correlation in their response to manufacturing process parameter perturbation and this is represented by a correlation matrix. Variation characterising data generated in accordance with the above technique is used to drive electronic design automation tools in integrated circuit design and manufacture.

Abstract: An integrated circuit 2 is formed of multiple wafer layers 4, 6, 8, 10 arranged in a stack and connected with through silicon vias 12. Mechanical strain sensors 26, 28, 30, 32 in the form of ring oscillators are provided proximal to the through silicon vias 12 and detect mechanical strain associated with the through silicon via 12. The measured mechanical strain may be used to dynamically adjust operating parameters of the integrated circuit either as a whole or in regions where the mechanical strain is detected. The operating parameters adjusted can include clock frequency, operating voltage and heat generation.

Abstract: An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus. The data processing apparatus includes a second sequential storage structure which is arranged to latch the output signal generated by combinatorial circuitry dependent on a second clock signal. The second sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry, and transition detection circuitry for detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct. The second sequential storage structure can be operated in either a first mode of operation or a second mode of operation.

Abstract: An integrated circuit is provided comprising at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory cells, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line.

Abstract: A static random access memory is disclosed.

Abstract: A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access control circuits each for controlling a voltage level supplied to a corresponding one of the at least two access control lines in response to an access request, the at least two access control circuits each comprising a capacitor and switching circuitry; routing circuitry for routing the access request and a boost signal to a selected one of the at least two access control circuits in dependence upon an address associated with the access request; wherein the at least two access control circuits are each responsive to: receipt of the access request from the routing circuitry to connect the selected access control line to a supply voltage; and receipt of the boost signal from the routing circuitry to disconnect the supply voltage from the access con

Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Abstract: An integrated circuit is provided with logic blocks which draw their power from virtual supply rails. These virtual supply rails are connected by switch blocks to main supply rails. The switch blocks are subject to modulation to maintain the virtual supply rails at an intermediate voltage level such that a reduced voltage difference is applied across the logic block. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks fully conductive and then the clock is restarted. The switch blocks which are modulated by controllers which use feedback control based upon the sensed virtual rail voltages (VVdd and Vgnd) while drawing their own power from the normal supply rails (Vdd and gnd).

Abstract: An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10, to the circuit block 38, 42, 44 in question and then back to the converter 10. Multiplexing circuitry 50, 52 associated with each serial scan chain loop 32, 34, 36 is used to either include that serial scan chain loop 32, 34, 36 in a combined serial scan chain or to bypass that serial scan chain loop 32, 34, 36. The circuit blocks 38, 42, 44 may be bypassed in this way if they are defective or if they are powered-down.

Abstract: A memory array comprising a plurality of rows and a plurality of columns, each row comprising at least one addressable word, said memory array comprising at least one redundant row and at least one redundant column; error detection circuitry for analysing said memory array, by addressing words within said memory array and detecting errors within said addressed words; error repair circuitry for selecting for a detected error either a redundant row or a redundant column to replace one of said row or column containing said error; wherein said error repair circuitry is configured to determine for said detected error whether said error is a single error bit in said addressed word or whether it is one of a plurality of error bits within said word, and if said error is said one of said plurality of errors, said error repair circuitry is configured to preferentially select a redundant row rather than a redundant column to repair said error.