Abstract: An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.

Abstract: A multiport memory 18, 20 is provided with multiple data access paths A, B, each having a respective independent clock signal CLKA, CLKB. During self test operation a duplicate clock enable signal DPCLKTESTEN is used to enable one of these clock signals CLKA, CLKB to be used as a shared clock signal by all data access paths A, B. An external memory adjust signal EMAA. EMAB is used to adjust one of these shared clock signals to form a modified shared clock signal for at least one of the data paths being tested. In this way, worst-case scenarios can be more readily investigated comprising clocks with the same frequency but small differences in phase.

Abstract: A technique for characterising variation in a performance parameter(s) of circuit cells within a circuit cell library with perturbations in manufacturing process parameters uses a statistical approach whereby the statistical distribution of performance parameter(s) resulting from a joint distribution across manufacturing process parameter space is determined. The perturbation in manufacturing process parameter which results in a characteristic amount of variation is then identified and common sets of such perturbations used to group families of circuit cells together. Families of circuit cells have a correlation in their response to manufacturing process parameter perturbation and this is represented by a correlation matrix. Variation characterising data generated in accordance with the above technique is used to drive electronic design automation tools in integrated circuit design and manufacture.

Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Abstract: An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10, to the circuit block 38, 42, 44 in question and then back to the converter 10. Multiplexing circuitry 50, 52 associated with each serial scan chain loop 32, 34, 36 is used to either include that serial scan chain loop 32, 34, 36 in a combined serial scan chain or to bypass that serial scan chain loop 32, 34, 36. The circuit blocks 38, 42, 44 may be bypassed in this way if they are defective or if they are powered-down.

Abstract: An integrated circuit 2 is provided with logic blocks 16 which draw their power from virtual supply rails 8, 10. These virtual supply rails 8, 10 are connected by switch blocks 12, 14 to main supply rails 4, 6. The switch blocks 12, 14 are subject to modulation to maintain the virtual supply rails 8, 10 at an intermediate voltage level such that a reduced voltage difference is applied across the logic block 16. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block 16 is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks 12, 14 fully conductive and then the clock is restarted.

Abstract: An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.