Patents by Inventor Robert L. Bristol
Robert L. Bristol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160172237Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.Type: ApplicationFiled: June 27, 2013Publication date: June 16, 2016Inventors: Robert L. Bristol, Rami HOURANI, Eungnak HAN, James M. BLACKWELL
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Publication number: 20160126184Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.Type: ApplicationFiled: November 3, 2015Publication date: May 5, 2016Inventors: Alan M. Myers, Kanwal Jit Singh, Robert L. Bristol, Jasmeet S. Chawla
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Publication number: 20160104642Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.Type: ApplicationFiled: December 10, 2015Publication date: April 14, 2016Inventors: Robert L. Bristol, Kevin Lin, Kanwal Jit Singh, Alan M. Myers, Richard E. Schenker
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Patent number: 9285682Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.Type: GrantFiled: March 9, 2015Date of Patent: March 15, 2016Assignee: Intel CorporationInventors: Robert L. Bristol, Paul A. Nyhus, Charles H. Wallace
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Patent number: 9236342Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.Type: GrantFiled: December 18, 2013Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: Robert L. Bristol, Kevin Lin, Kanwal Jit Singh, Alan M. Myers, Richard E. Schenker
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Patent number: 9209077Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.Type: GrantFiled: December 20, 2013Date of Patent: December 8, 2015Assignee: Intel CorporationInventors: Alan M. Myers, Kanwal Jit Singh, Robert L. Bristol, Jasmeet S. Chawla
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Publication number: 20150255284Abstract: Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.Type: ApplicationFiled: May 24, 2015Publication date: September 10, 2015Inventors: Robert L. Bristol, James M. Blackwell, Alan M. Myers, Kanwal Jit Singh
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Publication number: 20150253667Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.Type: ApplicationFiled: March 9, 2015Publication date: September 10, 2015Applicant: INTEL CORPORATIONInventors: ROBERT L. BRISTOL, PAUL A. NYHUS, CHARLES H. WALLACE
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Publication number: 20150179513Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: Alan M. Myers, Kanwal Jit Singh, Robert L. Bristol, Jasmeet S. Chawla
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Publication number: 20150171009Abstract: Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventors: Robert L. Bristol, James M. Blackwell, Alan M. Myers, Kanwal Jit Singh
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Publication number: 20150171010Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventors: Robert L. Bristol, Kevin Lin, Kanwal Jit Singh, Alan M. Myers, Richard E. Schenker
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Publication number: 20150170926Abstract: Embodiments of the present disclosure describe dielectric layers and methods for their fabrication and use. In some embodiments, a dielectric layer may include a dielectric material and a plurality of elongate pores. The dielectric material may have a first surface and an opposing second surface spaced away from the first surface in a direction defined by an axis, and may have a Young's modulus (E0) in the direction defined by the axis. Individual elongate pores of the plurality of elongate pores may extend from the second surface with a longitudinal axis substantially parallel to the axis. The plurality of elongate pores may provide the dielectric layer with a porosity, p, greater than approximately 30%, and the dielectric layer may have a Young's modulus approximately equal to E0*(1?p) in the direction defined by the axis. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 16, 2013Publication date: June 18, 2015Inventors: David J. Michalak, Robert L. Bristol, Arkaprabha Sengupta, Mauro J. Kobrinsky
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Publication number: 20150155349Abstract: Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.Type: ApplicationFiled: February 13, 2015Publication date: June 4, 2015Applicant: INTEL CORPORATIONInventors: Mauro J. Kobrinsky, Robert L. Bristol, Michael C. Mayberry
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Patent number: 9041217Abstract: Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.Type: GrantFiled: December 18, 2013Date of Patent: May 26, 2015Assignee: Intel CorporationInventors: Robert L. Bristol, James M. Blackwell, Alan M. Myers, Kanwal Jit Singh
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Patent number: 9005875Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.Type: GrantFiled: March 15, 2013Date of Patent: April 14, 2015Assignee: Intel CorporationInventors: Robert L. Bristol, Paul A. Nyhus, Charles H. Wallace
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Patent number: 8993404Abstract: Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.Type: GrantFiled: January 23, 2013Date of Patent: March 31, 2015Assignee: Intel CorporationInventors: Mauro J. Kobrinsky, Robert L. Bristol, Michael C. Mayberry
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Publication number: 20140272711Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: ROBERT L. BRISTOL, PAUL A. NYHUS, CHARLES H. WALLACE
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Publication number: 20140203400Abstract: Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.Type: ApplicationFiled: January 23, 2013Publication date: July 24, 2014Inventors: Mauro J. Kobrinsky, Robert L. Bristol, Michael C. Mayberry
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Patent number: 7825424Abstract: Methods to manufacture contaminant-gettering materials in the surface of EUV optics are described herein. An optical element is patterned and a contaminant-gettering material is formed on a surface of the optical element. In one embodiment, a photoresist is deposited on an optical coating on the optical element. Trenches are formed in the optical coating. The gettering agent is formed into the trenches over the photoresist. Next, the photoresist is removed from the optical coating to expose the gettering agent in the trenches. For another embodiment, patches of a nanotube forest having a gettering agent are formed in designated areas of an optical element. The gettering agent of the patches may be a plurality of carbon nanotubes. The optical coating is formed on a substrate between patches of the gettering agent.Type: GrantFiled: December 14, 2007Date of Patent: November 2, 2010Assignee: Intel CorporationInventors: Robert L. Bristol, Bruce H. Billett
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Publication number: 20080158662Abstract: Methods to manufacture contaminant-gettering materials in the surface of EUV optics are described herein. An optical element is patterned and a contaminant-gettering material is formed on a surface of the optical element. In one embodiment, a photoresist is deposited on an optical coating on the optical element. Trenches are formed in the optical coating. The gettering agent is formed into the trenches over the photoresist. Next, the photoresist is removed from the optical coating to expose the gettering agent in the trenches. For another embodiment, patches of a nanotube forest having a gettering agent are formed in designated areas of an optical element. The gettering agent of the patches may be a plurality of carbon nanotubes. The optical coating is formed on a substrate between patches of the gettering agent.Type: ApplicationFiled: December 14, 2007Publication date: July 3, 2008Inventors: Robert L. Bristol, Bruce H. Billett