Patents by Inventor Robert M. Toth

Robert M. Toth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190317599
    Abstract: A virtual reality apparatus and method are described.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Inventors: Tomas G. AKENINE-MOLLER, Robert M. TOTH, Ingo WALD, Aditya S. YANAMANDRA, Brent E. INSKO, Michael APODACA, Prasoonkumar SURTI
  • Patent number: 10445859
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Bjorn Johnsson, Jon N. Hasselgren
  • Patent number: 10446118
    Abstract: An apparatus and method are described for subdividing swap chains using partitions. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames; partition management logic to subdivide each of the image frames into at least two partitions and to designate each partition in each image frame as being in a front buffer or in a back buffer; the GPU to perform rendering operations to partitions designated as being in the back buffer; and a display link to concurrently perform a scan-out of scan lines from partitions designated as being in a front buffer.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventor: Robert M. Toth
  • Publication number: 20190259209
    Abstract: An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 22, 2019
    Inventors: Kalyan K. Bhiravabhatla, Subramaniam Maiyuran, Robert M. Toth, Tomasz Janczak
  • Patent number: 10379611
    Abstract: A virtual reality apparatus and method are described.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Ingo Wald, Aditya S. Yanamandra, Brent E. Insko, Michael Apodaca, Prasoonkumar Surti
  • Patent number: 10354432
    Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Jon N. Hasselgren, Franz P. Clarberg, Magnus Andersson, Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Moller
  • Publication number: 20190130527
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Applicant: Intel Corporation
    Inventors: Tomas G. AKENINE-MOLLER, Robert M. TOTH, Bjorn JOHNSSON, Jon N. HASSELGREN
  • Patent number: 10242286
    Abstract: An index is assigned to each entry in the set of possible coverage masks and two functions are generated. One function translates an index to a coverage mask. Also, a sparse function generates an index from a coverage mask. These functions may be realized in hardware and are used during decompression and compression, respectively.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Magnus Andersson, Robert M. Toth
  • Publication number: 20190087680
    Abstract: An index is assigned to each entry in the set of possible coverage masks and two functions are generated. One function translates an index to a coverage mask. Also, a sparse function generates an index from a coverage mask. These functions may be realized in hardware and are used during decompression and compression, respectively.
    Type: Application
    Filed: November 16, 2018
    Publication date: March 21, 2019
    Inventors: Jon N. Hasselgren, Magnus Andersson, Robert M. Toth
  • Patent number: 10235811
    Abstract: An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Kalyan K. Bhiravabhatla, Subramaniam Maiyuran, Robert M. Toth, Tomasz Janczak
  • Patent number: 10152820
    Abstract: Various embodiments provide for a new texture address mode that excludes any texture filter taps (i.e. coordinates) that fall outside the texture domain from the filtering process. Taps outside a texture domain are not considered in one embodiment. Also, various embodiments provide flexibility as to the texture coordinate locations ti and values of weights wi. The tap weight can be modified as a function of tap location and in particular whether a tap is within a texture.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Robert M. Toth, Tim Foley
  • Patent number: 10074213
    Abstract: An architecture for pixel shading, enables flexible control of shading rates and automatic shading reuse between triangles in tessellated primitives in some embodiments. The cost of pixel shading may then be decoupled from the geometric complexity. Wider use of tessellation and fine geometry may be made more feasible, even at very limited power budgets. Shading may be done over small local grids in parametric patch space, with reusing of shading for nearby samples. The decomposition of shaders into multiple parts is supported, which parts are shaded at different frequencies. Shading rates can be locally and adaptively controlled, in order to direct the computations to visually important areas and to provide performance scaling with a graceful degradation of quality. Another important benefit, in some embodiments, of shading in patch space is that it allows efficient rendering of distribution effects, which further closes the gap between real-time and offline rendering.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Franz P. Clarberg, Tomas G. Akenine-Moller, Robert M. Toth, Carl J. Munkberg
  • Publication number: 20180190021
    Abstract: An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Kalyan K. Bhiravabhatla, Subramaniam Maiyuran, Robert M. Toth, Tomasz Janczak
  • Patent number: 9990748
    Abstract: The adverse affects of using out-of-bounds texels for bilateral interpolation may be reduced by redefining the valid texel domain as having four corners defined at the centers of four corner texels. As a result, the texels around the periphery of the valid texture domain are partial texels, with the corner texels being one quarter of a texel and the edges being half of a texel.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Franz P. Clarberg, Robert M. Toth, Larry Seiler
  • Publication number: 20180082464
    Abstract: A graphics processing apparatus and method are described.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: TOMAS G. AKENINE-MOLLER, ROBERT M. TOTH, BRENT E. INSKO, PETER L. DOYLE, PRASOONKUMAR SURTI, MAIYURAN SUBRAMANIAM, CARL JACOB MUNKBERG, FRANZ PETRIK CLARBERG, JON N. HASSELGREN
  • Publication number: 20180082467
    Abstract: Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimization for texture-dependent discard operations are described. In an embodiment, a processor performs one or more operations (such as HiZ or Hierarchical Stencil test) on depth data of an image tile in response to a determination that texture space bounds of the image tile is fully opaque. The processor performs the one or more operations regardless of whether a discard operation is enabled. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Applicant: Intel Corporation
    Inventors: Magnus Andersson, Robert M. Toth, Jon N. Hasselgren, Tomas G. Akenine-Moller
  • Publication number: 20180081429
    Abstract: A virtual reality apparatus and method are described.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: TOMAS G. AKENINE-MOLLER, ROBERT M. TOTH, INGO WALD, ADITYA S. YANAMANDRA, BRENT E. INSKO, MICHAEL APODACA, PRASOONKUMAR SURTI
  • Publication number: 20180075573
    Abstract: Methods and apparatus relating to techniques for provision of minimum or maximum and bitwise logic AND or logic OR based coarse stencil tests are described. In an embodiment, metadata (corresponding to a plurality of pixels) is stored in memory. One or more operations are performed on the metadata to generate a stencil result. The one or more operations comprise a bitwise intersection operation or a bitwise union operation and/or a minimum operation or maximum operation. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 15, 2018
    Applicant: Intel Corporation
    Inventors: Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
  • Patent number: 9906816
    Abstract: A mechanism is described for facilitating environment-based lossy compression of data for efficient rendering of contents at computing devices. A method of embodiments, as described herein, includes collecting, in real time, sensory input data relating to characteristics of at least one of a user and a surrounding environment. The method may further include evaluating the sensory input data to mark one or more data portions of data relating to contents, where the one or more data portions are determined to be suitable for compression based on the sensory input data. The method may further include dynamically performing, in real time, the compression of the one or more data portions, where the compression triggers loss of one or more content portions of the contents corresponding to the one or more data portions of the data.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Moller, Franz P. Clarberg
  • Publication number: 20170372450
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Application
    Filed: July 10, 2017
    Publication date: December 28, 2017
    Inventors: TOMAS G. AKENINE-MOLLER, ROBERT M. TOTH, BJORN JOHNSSON, JON N. HASSELGREN