Patents by Inventor Robert M. Toth

Robert M. Toth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170243395
    Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.
    Type: Application
    Filed: January 4, 2017
    Publication date: August 24, 2017
    Inventors: Karthik Vaidyanathan, Marco Salvi, Robert M. Toth
  • Publication number: 20170206700
    Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 20, 2017
    Inventors: CARL J. MUNKBERG, JON N. HASSELGREN, FRANZ P. CLARBERG, MAGNUS ANDERSSON, ROBERT M. TOTH, JIM K. NILSSON, TOMAS G. AKENINE-MOLLER
  • Patent number: 9704217
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Bjorn Johnsson, Jon N. Hasselgren
  • Publication number: 20170154403
    Abstract: A mechanism is described for facilitating efficient processing of graphics data using triple buffered constant buffers at computing devices. A method of embodiments, as described herein, includes detecting generation of a multi-block buffer by an application to perform data processing at a graphics processor of a computing device, and mapping a first memory block of the multi-block buffer to the graphics processor, where mapping further includes mapping a second memory block and a third memory block of the multi-block buffer to an application processor. The method further includes executing a swap operation to facilitate the graphics processor to process a current data set associated with the application processor.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Applicant: INTEL CORPORATION
    Inventors: ROBERT M. TOTH, JON N. HASSELGREN
  • Publication number: 20170142447
    Abstract: A mechanism is described for facilitating environment-based lossy compression of data for efficient rendering of contents at computing devices. A method of embodiments, as described herein, includes collecting, in real time, sensory input data relating to characteristics of at least one of a user and a surrounding environment. The method may further include evaluating the sensory input data to mark one or more data portions of data relating to contents, where the one or more data portions are determined to be suitable for compression based on the sensory input data. The method may further include dynamically performing, in real time, the compression of the one or more data portions, where the compression triggers loss of one or more content portions of the contents corresponding to the one or more data portions of the data.
    Type: Application
    Filed: October 19, 2016
    Publication date: May 18, 2017
    Inventors: ROBERT M. TOTH, JIM K. NILSSON, TOMAS G. AKENINE-MOLLER, FRANZ P. CLARBERG
  • Patent number: 9569886
    Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. An algorithm may be used to determine how the shading rate changes across the frame.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Karthik Vaidyanathan, Marco Salvi, Robert M. Toth, Aaron Lefohn
  • Patent number: 9569883
    Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Karthik Vaidyanathan, Marco Salvi, Robert M. Toth
  • Publication number: 20160358299
    Abstract: An apparatus and method are described for subdividing swap chains using partitions. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames; partition management logic to subdivide each of the image frames into at least two partitions and to designate each partition in each image frame as being in a front buffer or in a back buffer; the GPU to perform rendering operations to partitions designated as being in the back buffer; and a display link to concurrently perform a scan-out of scan lines from partitions designated as being in a front buffer.
    Type: Application
    Filed: June 2, 2015
    Publication date: December 8, 2016
    Inventor: ROBERT M. TOTH
  • Patent number: 9501864
    Abstract: Because using the same number of bits per residual depth offset compression is not the best distribution of bits, the bits per residual may be distributed instead according to the content of the depths of a tile. For example, if the depth differences close to the Zmax are small, then fewer bits can be spent on residuals for the samples that are encoded relative to Zmax. Consequently, more bits can be spent on the residuals for the samples that are encoded relative to Zmin. As a result, more tiles succeed at compressing to the required number of bits.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Magnus Andersson, Jon N. Hasselgren, Carl J. Munkberg, Robert M. Toth
  • Patent number: 9491490
    Abstract: A mechanism is described for facilitating environment-based lossy compression of data for efficient rendering of contents at computing devices. A method of embodiments, as described herein, includes collecting, in real time, sensory input data relating to characteristics of at least one of a user and a surrounding environment. The method may further include evaluating the sensory input data to mark one or more data portions of data relating to contents, where the one or more data portions are determined to be suitable for compression based on the sensory input data. The method may further include dynamically performing, in real time, the compression of the one or more data portions, where the compression triggers loss of one or more content portions of the contents corresponding to the one or more data portions of the data.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Möller, Franz P. Clarberg
  • Patent number: 9465212
    Abstract: User-controllable defocus blur for a stochastic rasterizer may be implemented by modifying circle of confusion coefficients per vertex to express more general defocus blur. The method can be applied to limit the foreground blur, extend the in-focus range, simulate tilt-shift photography, and specify per-object defocus blur. Furthermore, with two simplifying assumptions, existing triangle coverage tests and tile culling tests can be used with very modest modifications.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: October 11, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Robert M. Toth
  • Publication number: 20160284120
    Abstract: An index is assigned to each entry in the set of possible coverage masks and two functions are generated. One function translates an index to a coverage mask. Also, a sparse function generates an index from a coverage mask. These functions may be realized in hardware and are used during decompression and compression, respectively.
    Type: Application
    Filed: March 25, 2015
    Publication date: September 29, 2016
    Inventors: Jon N. Hasselgren, Magnus Andersson, Robert M. Toth
  • Publication number: 20160275701
    Abstract: The adverse affects of using out-of-bounds texels for bilateral interpolation may be reduced by redefining the valid texel domain as having four corners defined at the centers of four corner texels. As a result, the texels around the periphery of the valid texture domain are partial texels, with the corner texels being one quarter of a texel and the edges being half of a texel.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 22, 2016
    Inventors: Franz P. Clarberg, Robert M. Toth, Larry Seiler
  • Patent number: 9406100
    Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles whose triangles have been vertex shaded and binned over tiles whose triangles have yet to be vertex shaded and binned. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 9401046
    Abstract: Micropolygon splatting may involve tessellating by subdividing a mesh until triangle edges are shorter than 0.75 pixels. In some cases, rasterizing the primitive may be avoided.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: July 26, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Tomas G. Akenine-Möller, Jon N. Hasselgren, Robert M. Toth
  • Patent number: 9390541
    Abstract: In accordance with some embodiments, a tile shader executes on a group of pixels prior to a pixel shader. The tile of pixels may be rectangular in some embodiments. The tile may be executed hierarchically, refining each tile into smaller subtiles until the pixel or sample level is reached. The tile shader program can be written to discard groups of pixels, thereby quickly removing areas of the bounding triangles that lie outside the shape being rasterized or quickly discarding groups of pixel shader executions that will not contribute to the final image.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Jim K. Nilsson, Robert M. Toth, Franz P. Clarberg
  • Patent number: 9317964
    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Jon N. Hasselgren, Robert M. Toth
  • Publication number: 20160055614
    Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles whose triangles have been vertex shaded and binned over tiles whose triangles have yet to be vertex shaded and binned. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
    Type: Application
    Filed: November 3, 2015
    Publication date: February 25, 2016
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20160054790
    Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Inventors: Tomas G. Akenine-Moller, Bjorn Johnsson, Magnus Andersson, Jim K. Nilsson, Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
  • Patent number: 9262841
    Abstract: In one embodiment, pixels that cannot change their color due to the alpha blend mode and the color already stored in a render target are detected. For example, if destination alpha blending is used and a target pixel has an alpha value of 1.0, it will not change color regardless of the computed color of subsequently composited objects. Both computing the object colors and accessing the frame buffer can be avoided when such a case is detected. This may save computations and bandwidth in some embodiments.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventor: Robert M. Toth