Patents by Inventor Robert M. Toth

Robert M. Toth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9201487
    Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Bjorn Johnsson, Magnus Andersson, Jim K. Nilsson, Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
  • Patent number: 9183608
    Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles that have been vertex shaded and binned triangles over tiles that have yet to be vertex shaded and binned triangles. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 9165348
    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Robert M. Toth, Tomas G. Akenine-Moller, Carl J. Munkberg
  • Publication number: 20150287238
    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 8, 2015
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Jon N. Hasselgren, Robert M. Toth
  • Publication number: 20150187124
    Abstract: Because using the same number of bits per residual depth offset compression is not the best distribution of bits, the bits per residual may be distributed instead according to the content of the depths of a tile. For example, if the depth differences close to the Zmax are small, then fewer bits can be spent on residuals for the samples that are encoded relative to Zmax. Consequently, more bits can be spent on the residuals for the samples that are encoded relative to Zmin. As a result, more tiles succeed at compressing to the required number of bits.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Inventors: Tomas G. Akenine-Moller, Magnus Andersson, Jon N. Hasselgren, Carl J. Munkberg, Robert M. Toth
  • Publication number: 20150178983
    Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. An algorithm may be used to determine how the shading rate changes across the frame.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 25, 2015
    Inventors: Tomas G. Akenine-Moller, Karthik Vaidyanathan, Marco Salvi, Robert M. Toth, Aaron Lefohn
  • Publication number: 20150170345
    Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Inventors: Karthik Vaidyanathan, Marco Salvi, Robert M. Toth
  • Patent number: 9058697
    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: June 16, 2015
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Möller, Carl J. Munkberg, Jon N. Hasselgren, Robert M. Toth
  • Publication number: 20150145873
    Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles that have been vertex shaded and binned triangles over tiles that have yet to be vertex shaded and binned triangles. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
    Type: Application
    Filed: December 23, 2009
    Publication date: May 28, 2015
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20150138226
    Abstract: In one embodiment, pixels that cannot change their color due to the alpha blend mode and the color already stored in a render target are detected. For example, if destination alpha blending is used and a target pixel has an alpha value of 1.0, it will not change color regardless of the computed color of subsequently composited objects. Both computing the object colors and accessing the frame buffer can be avoided when such a case is detected. This may save computations and bandwidth in some embodiments.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Inventor: Robert M. Toth
  • Patent number: 9038034
    Abstract: During compilation, the interval bounds for a programmable culling unit are calculated if possible. For each variable, interval bounds are calculated during the compilation, and the bounds together with other metadata are used to generate an optimized culling program. If not possible, then an assumption may be made and the assumption used to compile the code. If the assumption proves to be invalid, a new assumption could be made and the code may be recompiled in some embodiments.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg, Robert M. Toth
  • Publication number: 20150070355
    Abstract: An architecture for pixel shading, enables flexible control of shading rates and automatic shading reuse between triangles in tessellated primitives in some embodiments. The cost of pixel shading may then be decoupled from the geometric complexity. Wider use of tessellation and fine geometry may be made more feasible, even at very limited power budgets. Shading may be done over small local grids in parametric patch space, with reusing of shading for nearby samples. The decomposition of shaders into multiple parts is supported, which parts are shaded at different frequencies. Shading rates can be locally and adaptively controlled, in order to direct the computations to visually important areas and to provide performance scaling with a graceful degradation of quality. Another important benefit, in some embodiments, of shading in patch space is that it allows efficient rendering of distribution effects, which further closes the gap between real-time and offline rendering.
    Type: Application
    Filed: March 27, 2014
    Publication date: March 12, 2015
    Inventors: Franz P. Clarberg, Tomas G. Akenine-Moller, Robert M. Toth, Carl J. Munkberg
  • Publication number: 20140300619
    Abstract: In accordance with some embodiments, a tile shader executes on a group of pixels prior to a pixel shader. The tile of pixels may be rectangular in some embodiments. The tile may be executed hierarchically, refining each tile into smaller subtiles until the pixel or sample level is reached. The tile shader program can be written to discard groups of pixels, thereby quickly removing areas of the bounding triangles that lie outside the shape being rasterized or quickly discarding groups of pixel shader executions that will not contribute to the final image.
    Type: Application
    Filed: April 9, 2013
    Publication date: October 9, 2014
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Jim K. Nilsson, Robert M. Toth, Franz P. Clarberg
  • Patent number: 8842121
    Abstract: A single instruction multiple data (SIMD) processor with a given width may operate on registers of the same width completely filled with fragments. A parallel set of registers are loaded and tested. The fragments that fail are eliminated and the register set is refilled from the parallel set.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Tomas Akenine-Möller, Jon N. Hasselgren, Carl J. Munkberg, Robert M. Toth, Franz P. Clarberg
  • Publication number: 20140267345
    Abstract: Various embodiments provide for a new texture address mode that excludes any texture filter taps (i.e. coordinates) that fall outside the texture domain from the filtering process. Taps outside a texture domain are not considered in one embodiment. Also, various embodiments provide flexibility as to the texture coordinate locations ti and values of weights wi. The tap weight can be modified as a function of tap location and in particular whether a tap is within a texture.
    Type: Application
    Filed: December 17, 2013
    Publication date: September 18, 2014
    Inventors: Robert M. Toth, Tim Foley
  • Publication number: 20140258754
    Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Inventors: Tomas G. Akenine-Moller, Bjorn Johnsson, Magnus Andersson, Jim K. Nilsson, Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
  • Patent number: 8587585
    Abstract: In order to efficiently backface cull rendering primitives during computer graphics rendering, it is important to be sure that the rendering primitives to be culled are guaranteed to be backfacing even if the primitives are moving or are undergoing defocus blur. Therefore, we derive conservative tests that determine if a moving and defocused triangle is backfacing over an entire time interval and over the area of a lens. In addition, we present tests for the special cases of only motion blur and only depth of field.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: November 19, 2013
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Tomas G. Akenine-Möller, Marco Salvi, Robert M. Toth, Jon N. Hasselgren, Franz P. Clarberg, Matt Pharr
  • Publication number: 20130287314
    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
    Type: Application
    Filed: November 21, 2011
    Publication date: October 31, 2013
    Inventors: Robert M. Toth, Tomas G. Akenine-Moller, Carl J. Munkberg
  • Publication number: 20130271465
    Abstract: A graphics pipeline combines the benefits of decoupling sampling with deferred shading. In the rasterization phase, a shading point is computed for each sample. After rasterization is finished, the shading points are sorted to extract coherence and groups of shading points shaded. This enables high sampling rates with efficient reuse of shading, in addition to other unique benefits.
    Type: Application
    Filed: December 30, 2011
    Publication date: October 17, 2013
    Inventors: Franz P. Clarberg, Robert M. Toth, Karthik Vaidyanathan
  • Publication number: 20130257866
    Abstract: User-controllable defocus blur for a stochastic rasterizer may be implemented by modifying circle of confusion coefficients per vertex to express more general defocus blur. The method can be applied to limit the foreground blur, extend the in-focus range, simulate tilt-shift photography, and specify per-object defocus blur. Furthermore, with two simplifying assumptions, existing triangle coverage tests and tile culling tests can be used with very modest modifications.
    Type: Application
    Filed: July 5, 2012
    Publication date: October 3, 2013
    Inventors: Carl J. Munkberg, Robert M. Toth