Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

Abstract: A number of variations may include a turbine housing comprising a turbine body; an inlet passage and an outlet passage connected to the turbine body; a wastegate passage operatively connected to the outlet passage; a diffuser positioned within the outlet passage comprising at least one radial opening; wherein the first flow passage accepts fluid flow from the wastegate passage and the second flow passage accepts fluid flow from the turbine wheel; wherein a first end of the diffuser is attached to a first end of the turbine outlet and a second end of the diffuser is attached to a second end of the turbine outlet so that fluid flow from the first flow passage is directed into the second flow passage through the at least one radial opening before exiting the outlet passage, and wherein the at least one radial opening minimizes turbulence of fluid flow exiting the turbine housing.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

Abstract: A number of variations may include a turbine housing comprising a turbine body; an inlet passage and an outlet passage connected to the turbine body; a wastegate passage operatively connected to the outlet passage; a diffuser positioned within the outlet passage comprising at least one radial opening; wherein the first flow passage accepts fluid flow from the wastegate passage and the second flow passage accepts fluid flow from the turbine wheel; wherein a first end of the diffuser is attached to a first end of the turbine outlet and a second end of the diffuser is attached to a second end of the turbine outlet so that fluid flow from the first flow passage is directed into the second flow passage through the at least one radial opening before exiting the outlet passage, and wherein the at least one radial opening minimizes turbulence of fluid flow exiting the turbine housing.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

Abstract: A Schottky barrier device is provided herein that includes a TMD layer on a substrate, a graphene layer on the TMD layer, an electrolyte layer on the TMD layer, and a source gate contact on the electrolyte layer. A drain contact can be provided on the TMD layer and a source contact can be provided on the graphene layer. As ionic gating from the source gate contact and electrolyte layer is used to adjust the Schottky barrier height this Schottky barrier device can be referred to as an ionic control barrier transistor or “ionic barristor”.

Abstract: A Schottky barrier device is provided herein that includes a TMD layer on a substrate, a graphene layer on the TMD layer, an electrolyte layer on the TMD layer, and a source gate contact on the electrolyte layer. A drain contact can be provided on the TMD layer and a source contact can be provided on the graphene layer. As ionic gating from the source gate contact and electrolyte layer is used to adjust the Schottky barrier height this Schottky barrier device can be referred to as an ionic control barrier transistor or “ionic barristor”.

Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

Abstract: A method is provided, the method comprising operating a field emitter array (FEA) to generate at least one of a high electric field and a high electron flux, and exposing the field emitter array (FEA) to at least one gas. The method further comprises generating at least one radical species from the at least one gas exposed to the at least one of the high electric field and the high electron flux.

Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.

Abstract: This invention pertains generally to forming thin oxides at low temperatures, and more particularly to forming uniformly thick, thin oxides. We disclose a low temperature method for forming a thin, uniform oxide 16 on a silicon surface 12. This method includes providing a partially completed integrated circuit on a semiconductor substrate 10 with a clean, hydrogen terminated or atomically flat, silicon surface 12; and stabilizing the substrate at a first temperature. The method further includes exposing the silicon surface to an atmosphere 14 including ozone, while maintaining the substrate 10 at the first temperature. In this method, the exposing step creates a uniformly thick, oxide film 16. This method is suitable for room temperature processing.

Abstract: A method of processing a substrate is disclosed. The method includes depositing a dielectric layer having a metal oxide on a substrate. A portion of the dielectric layer is removed to form a dielectric structure, thereby exposing a surface of the substrate. For example, the dielectric layer may be patterned using standard photolithographic techniques and etching. An oxide layer is then formed on the exposed surface of the substrate. The oxide layer may be formed using ozone that is generated using ultraviolet radiation. After the oxide layer is formed, it is removed using an etching process.

Abstract: An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method comprising: providing the second structure; forming the electrically conductive structure of a material (step 118 of FIG. 1) that remains substantially conductive after it is oxidized; forming an electrically insulative layer (step 116 of FIG. 1) between the second structure and the conductive structure; and oxidizing the conductive structure by subjecting it to an ozone containing atmosphere for a duration of time and at a first temperature.

Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.

Abstract: CMOS and BiCMOS structures with a silicate-germanate gate dielectric on SiGe PMOS areas and Si NMOS areas plus HBTs with Si—SiGe emitter-base junctions.

Abstract: A method of processing a substrate is disclosed. The method includes depositing a dielectric layer having a metal oxide on a substrate. A portion of the dielectric layer is removed to form a dielectric structure, thereby exposing a surface of the substrate. For example, the dielectric layer may be patterned using standard photolithographic techniques and etching. An oxide layer is then formed on the exposed surface of the substrate. The oxide layer may be formed using ozone that is generated using ultraviolet radiation. After the oxide layer is formed, it is removed using an etching process.