Patents by Inventor Robert M. Wallace

Robert M. Wallace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6730977
    Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, John Mark Anthony, Yi Wei, Robert M. Wallace
  • Publication number: 20030207590
    Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.
    Type: Application
    Filed: June 3, 2003
    Publication date: November 6, 2003
    Inventors: Glen D. Wilk, John Mark Anthony, Yi Wei, Robert M. Wallace
  • Patent number: 6624944
    Abstract: A protective cover (10) for an optical device, such as a spatial light modulator or an infrared detector or receiver. The cover (10) has an optically transmissive window (11), which has a coating (12) on one or both of its surfaces. The coating (12) is made from a halogenated material, which is deposited to form a chemical bond with the surface of the window (11).
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: September 23, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Marvin W. Cowens, Steven A. Henck
  • Patent number: 6613698
    Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: September 2, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, John Mark Anthony, Yi Wei, Robert M. Wallace
  • Publication number: 20030136660
    Abstract: A method is provided, the method comprising operating a field emitter array (FEA) to generate at least one of a high electric field and a high electron flux, and exposing the field emitter array (FEA) to at least one gas. The method further comprises generating at least one radical species from the at least one gas exposed to the at least one of the high electric field and the high electron flux.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Inventors: Bruce A. Gnade, Robert M. Wallace
  • Patent number: 6552388
    Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: April 22, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, Robert M. Wallace
  • Publication number: 20030062586
    Abstract: CMOS and BiCMOS structures with a silicate-germanate gate dielectric on SiGe PMOS areas and Si NMOS areas plus HBTs with Si—SiGe emitter-base junctions.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 3, 2003
    Inventors: Robert M. Wallace, Bruce E. Gnade
  • Publication number: 20020177293
    Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.
    Type: Application
    Filed: June 14, 2002
    Publication date: November 28, 2002
    Inventors: Glen D. Wilk, Robert M. Wallace
  • Patent number: 6468856
    Abstract: An integrated circuit capacitor comprising a high permittivity dielectric and a method of forming the same are disclosed herein. In one embodiment, this capacitor may be used as a DRAM storage cell. For example, a DRAM storage node electrode 22 may be formed of polysilicon. An ultrathin oxynitride passivation layer 25 (e.g. less than 1 nm) is formed on this electrode by exposure of the substrate to NO. A tantalum pentoxide layer 24 is formed over layer 25, followed by a cell plate 26. Passivation layer 25 allows electrode 22 to resist oxidation during deposition of layer 25, thus preventing formation of an interfacial oxide layer. A passivation layer formed by this method may typically be deposited with shorter exposure times and lower temperatures than nitride passivation layers.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: October 22, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Glen D. Wilk, Mark Anthony, Dim-Lee Kwong
  • Patent number: 6436801
    Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: August 20, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, Robert M. Wallace
  • Patent number: 6420729
    Abstract: A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: July 16, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Glen D. Wilk, Yi Wei, Sunil V. Hattangady
  • Publication number: 20020025626
    Abstract: This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer. Applications for high permittivity memory cells and gate dielectrics are disclosed. This method has steps of providing a partially completed integrated circuit having a semiconductor layer substantially comprising silicon, where the layer has an exposed face. The method also includes forming an ultra-thin SiC reaction barrier at the exposed face, and depositing a high permittivity storage dielectric on the SiC reaction barrier. Typically, the SiC reaction barrier is less than 25 Å thick, preferably one or two monolayers of SiC.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 28, 2002
    Inventors: Sunil Hattangady, Robert M. Wallace, Bruce E. Gnade, Yasutoshi Okuno
  • Patent number: 6335238
    Abstract: This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer. Applications for high permittivity memory cells and gate dielectrics are disclosed. This method has steps of providing a partially completed integrated circuit having a semiconductor layer substantially comprising silicon, where the layer has an exposed face. The method also includes forming an ultra-thin SiC reaction barrier at the exposed face, and depositing a high permittivity storage dielectric on the SiC reaction barrier. Typically, the SiC reaction barrier is less then 25 Å thick, preferably one or two monolayers of SiC.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: January 1, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Sunil V. Hanttangady, Robert M. Wallace, Bruce E. Gnade, Yasutoshi Okuno
  • Publication number: 20010053593
    Abstract: An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method comprising: providing the second structure; forming the electrically conductive structure of a material (step 118 of FIG. 1) that remains substantially conductive after it is oxidized; forming an electrically insulative layer (step 116 of FIG. 1) between the second structure and the conductive structure; and oxidizing the conductive structure by subjecting it to an ozone containing atmosphere for a duration of time and at a first temperature.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 20, 2001
    Inventors: Glen D. Wilk, Robert M. Wallace, John M. Anthony, Paul McIntyre
  • Publication number: 20010024853
    Abstract: An integrated circuit capacitor comprising a high permittivity dielectric and a method of forming the same are disclosed herein. In one embodiment, this capacitor may be used as a DRAM storage cell. For example, a DRAM storage node electrode 22 may be formed of polysilicon. An ultrathin oxynitride passivation layer 25 (e.g. less than 1 nm) is formed on this electrode by exposure of the substrate to NO. A tantalum pentoxide layer 24 is formed over layer 25, followed by a cell plate 26. Passivation layer 25 allows electrode 22 to resist oxidation during deposition of layer 25, thus preventing formation of an interfacial oxide layer. A passivation layer formed by this method may typically be deposited with shorter exposure times and lower temperatures than nitride passivation layers.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 27, 2001
    Inventors: Robert M. Wallace, Glen D. Wilk, Mark Anthony, Dim-Lee Kwong
  • Publication number: 20010023115
    Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.
    Type: Application
    Filed: May 17, 2001
    Publication date: September 20, 2001
    Inventors: Glen D. Wilk, John M. Anthony, Yi Wei, Robert M. Wallace
  • Patent number: 6291866
    Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: September 18, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Richard A. Stoltz, Glen D. Wilk
  • Patent number: 6291867
    Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) silicon-oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium silicon-oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium silicon-oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide. However, the zirconium silicon-oxynitride gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: September 18, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Richard A. Stoltz, Glen D. Wilk
  • Patent number: 6277681
    Abstract: A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: August 21, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Glen D. Wilk, Yi Wei, Sunil V. Hattangady
  • Patent number: 6274510
    Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: August 14, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, John Mark Anthony, Yi Wei, Robert M. Wallace