Abstract: The various implementations described herein include systems, methods and/or devices used to transfer data within a storage device. In one aspect, a method includes reading data from a first non-volatile memory device to a shared bus, where the shared bus couples the first non-volatile memory device to a second non-volatile memory device and to the controller, and where the first non-volatile memory device is on a first die and the second non-volatile memory device is on a second die, distinct from the first die. The method further includes, in conjunction with reading the data from the first non-volatile memory device to the shared bus, generating a data strobe at the first non-volatile memory device; and, in response to receiving the data strobe at the second non-volatile memory device, transferring the data from the shared bus to the second non-volatile memory device.

Abstract: A method of operation in a non-volatile memory system includes starting execution of a first memory operation from a first queue and in conjunction with starting a first timer, set to expire after a first predetermined time interval. The method further includes, in accordance with a determination that the first timer has expired, determining whether a second queue contains at least one memory operation for execution, and if so, suspending the first memory operation, executing a second memory operation from the second queue, and after completing execution of the second memory operation from the second queue, performing one or more subsequent operations (e.g., resuming execution of the first memory operation and restarting the first timer). In addition, the method includes, when the second queue does not contain at least one memory operation for execution, restarting the first timer, and continuing execution of the first memory operation from the first queue.

Abstract: Various embodiments described herein include systems, methods and/or devices used to dissipate heat generated by electronic components in an electronic system (e.g., a memory system including closely spaced memory modules). Specifically, a heat sink includes an attachment structure and a tab. The attachment structure defines a slot configured to receive an edge of a substrate and thermally couple to a ground plane of the substrate. The tab is located opposite to the slot, and is configured to slide into a card guide slot of an assembly rack, such that in use, heat generated by at least one electronic component on the substrate is at least partially transferred through the ground plane to the attachment structure to be dissipated.

Abstract: A method of operation in a non-volatile memory system for deferring, in accordance with a determination to reduce power consumption by the non-volatile memory system, execution of commands in a command queue corresponding to a distinct set of non-volatile memory devices during a respective wait period. In some implementations, the respective wait period for a first distinct set of non-volatile memory devices in at least two distinct sets is at least partially non-overlapping with the respective wait period for a second distinct set of non-volatile memory devices in the at least two distinct sets.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable power inrush management of storage devices (e.g., DIMM devices). In one aspect, the method includes, for at least one storage device populated in a slot of a plurality of storage device slots, the plurality of storage device slots configured to be populated by two or more storage devices: (1) detecting a unique location associated with the storage device, (2) determining a time delay for the storage device in accordance with the unique location associated with the storage device, and (3) delaying at least one power-on operation of the storage device by the time delay for the storage device.

Abstract: The various embodiments described herein include methods and/or systems for throttling power in a storage device. In one aspect, a method of operation in a storage system includes obtaining a power metric corresponding to a count of active memory commands in the storage system, where active memory commands are commands being executed by the storage system. The method further includes, in accordance with a determination that the power metric satisfies one or more power thresholds, deferring execution of one or more pending memory commands.

Abstract: Systems and methods disclosed herein are used to efficiently manage low read data. In one aspect, a method includes, in response to detecting occurrence of a first event (e.g., PFail), writing low read data to non-volatile memory of a storage device with a fast SLC programming mode, distinct from a default SLC programming mode. Writing the low read data with the fast SLC programming mode: (i) includes using one or more memory programming parameters distinct from a default set of memory programming parameters used for writing data with the default SLC programming mode and (ii) takes less time per predefined unit of data than writing data with the default SLC programming mode. The method also includes: in response to detecting occurrence of a second event (e.g., host write command), writing data corresponding to the second event with the default SLC programming mode using the default set of memory programming parameters.

Abstract: The system for redirecting airflow includes multiple electronic assemblies arranged adjacent to one another. Each electronic assembly includes a substrate having a substantially flat first surface and an opposing substantially flat second surface. Electronic devices are coupled to each of the first and second surfaces. Each surface also has one or more tabs coupled thereto, where each tab is configured to redirect the airflow over a least one electronic device.

Abstract: A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module, coupled to the power-down module, for estimating a power-off decay rate upon the memory sub-system powered up, the power-off decay rate is for indicating how much data in the memory sub-system has decayed while the memory sub-system has been powered down; and a recycle module, coupled to the decay estimation module, for recycling an erase block for data retention based on the power-off decay rate.

Abstract: Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable performing supervisory functions for a dual in-line memory module (DIMM), at a controller in the DIMM. The method includes upon power-up, determining a power supply voltage provided to the DIMM. In accordance with a determination that power supply criteria are satisfied, the method includes: (1) performing one or more power-up operations, including initiating a usage counter, (2) monitoring a temperature of the DIMM, (3) monitoring the DIMM for occurrence of one or more of a set of predetermined trigger events, and (4) in response to detecting one of the set of predetermined trigger events, logging information corresponding to the detected predetermined event.

Abstract: Various embodiments described herein include systems, methods and/or devices for dissipating heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic assembly includes a first circuit board, a second circuit board flexibly coupled to the first circuit board, a connecting module coupled to the second circuit board, and a fastener. The fastener is configured to couple the first circuit board to the connecting module such that the first circuit board and the second circuit board are substantially parallel and are separated by a space, wherein the space forms at least part of a channel that is configured to direct airflow through the space between the first circuit board, second circuit board, and connecting module.

Abstract: Various embodiments described herein include systems, methods and/or devices used to dissipate heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic system includes a substrate, at least one electronic component, and a heat sink. The at least one electronic component is mechanically coupled to the substrate and thermally coupled to a ground plane of the substrate, such that heat generated by the at least one electronic component is dissipated at least partially to the ground plane of the substrate. The heat sink is mechanically coupled to an edge of the substrate, and thermally coupled to the ground plane of the substrate to at least partially dissipate the heat generated by the at least one electronic component. In some embodiments, the heat sink further includes an attachment structure, a tab and a plurality of heat dissipaters.

Abstract: Various embodiments described herein disclose systems, methods and/or devices used to dissipate heat generated by electronic components of an electronic assembly that further includes a first assembly rail, a top circuit board and a bottom circuit board. The first assembly rail includes a first card guide structure and a second card guide structure that are arranged on a first side of the first assembly rail near two opposite ends of the assembly rail. The top and the bottom circuit boards are mechanically coupled to the first and second card guide structures of the first assembly rail, respectively. The top circuit board is parallel to the bottom circuit board, and separated from the bottom circuit board by a predefined distance. The first assembly rail, the top circuit board and the bottom circuit board together form a channel there between for receiving a heat dissipating airflow.

Abstract: Systems, methods, and/or devices are used to automate read operations performed at an open erase block. In one aspect, the method includes: receiving a read command, at a storage device, to read data from non-volatile memory of the storage device. In response to receiving the read command, the method further includes: 1) reading data using a first set of memory operation parameters in response to a determination that the read command is not for reading data from a predefined portion of an open erase block (e.g., an erase block that is determined to be an open erase block) of the non-volatile memory and 2) reading data using a second set of memory operation parameters (i.e., the second set is distinct from the first set) in response to a determination that the read command is for reading data from the predefined portion of an open erase block of the non-volatile memory.

Abstract: Systems, methods, and/or devices are used to manage high-priority NAND operations. In some embodiments, the method includes receiving a first command (e.g., requesting a high-priority memory operation) corresponding to a first location (e.g., having both a first physical address and a first aliased physical address) in a first die of a plurality of physical non-volatile memory die in a storage device. If the first die is performing a blocking low-priority memory operation (e.g., the low-priority operation was sent to the first die using a second physical address), the method includes sending a memory operation command, corresponding to the first memory operation, to the first die using the first aliased physical address. In some embodiments, a predefined die-selection portion of the second physical address matches the predefined die-selection portion of the first physical address and does not match the predefined die-selection portion of the first aliased physical address.

Abstract: A test system, and a method of manufacture thereof, including: a thermal management head including a heat spreader; an electronic device in direct contact with the heat spreader; and an electrical current for transferring energy between the heat spreader and the electronic device.

Abstract: A method of fault testing in a storage device comprises testing, in accordance with a storage device testing protocol, operability of a plurality of distinct portions on the storage device. The testing includes, for each of the plurality of distinct portions on the storage device: performing one or more operations on a respective portion of the storage device; recording data corresponding to electrical current drawn during performance of the one or more operations on the respective portion of the storage device; analyzing the recorded data, including determining whether one or more predefined characteristics of the recorded data meets predetermined failure criteria; and, in accordance with a determination that the recorded data meets the predetermined failure criteria, performing one or more remedial actions including updating a mapping of the storage device to mark the respective portion as a known-bad portion.

Abstract: A method of fault detection includes, while in normal operation: recording data corresponding to measurements of electrical current drawn during performance of a respective operation on a specified portion of a storage device; analyzing the recorded data, including determining whether one or more predefined characteristics of the recorded data meets predetermined failure criteria; and in accordance with a determination that the recorded data meets the predetermined failure criteria, performing one or more remedial actions, the one or more remedial actions including marking the specified portion as a known-bad portion.

Abstract: The various embodiments described herein include circuits, methods and/or devices used to protect data in a storage device. In one aspect, a method includes performing a power fail operation on a first section of the storage device. The power fail operation includes supplying power, via an energy storage device, to the first section of the storage device, where the energy storage device is distinct from a power source used during normal operation of the storage device, and where supplying power via the energy storage device includes switching the output of the energy storage device from an output of a boost regulator to an input of the boost regulator. The power fail operation also includes performing data hardening on the first section of the storage device.