Abstract: The various implementations described herein include systems, methods and/or devices used to protect data in a storage device. In one aspect, a method includes (1) powering a power control processor (PCP) (also sometimes called a storage-level microcontroller) using a first input voltage, (2) while the PCP is powered using the first input voltage: (a) operating the PCP in a first mode, and (b) enabling charging of an energy storage device, (3) after achieving a predefined internal state, which includes the energy storage device charged to a predefined level, powering the PCP using a power supply voltage distinct from the first input voltage, and (4) while the PCP is powered using the power supply voltage, operating the PCP in a second mode, where the PCP operates at a higher performance level in the second mode than in the first mode.

Abstract: An electronic device includes a subsystem, a plurality of energy storage elements coupled to the subsystem through one or more switches, and a charging and monitoring apparatus for concurrently charging the plurality of energy storage elements and monitoring operability of the energy storage elements. A first subset of the energy storage elements is coupled to a first node and a second subset of the energy storage elements is coupled to a second node of a bridge circuit. A power supply provides a DC charging voltage and an AC test voltage to both the first and second subsets of the energy storage elements. A monitoring circuit produces a predefined fault signal if a predefined electrical characteristic of the first subset of the energy storage elements differs from a same predefined electrical characteristic of the second subset of the energy storage elements by more than a predefined amount.

Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.

Abstract: A storage device and method for performing a self-refresh operation are disclosed. In one embodiment, a storage device determines that the self-refresh operation needs to be performed. In response to that determination, the storage device performs the self-refresh operation by reading data from the memory and writing the data back to the memory without transferring the data outside of the storage device.

Abstract: A method of operation of a storage control system includes: calculating a throttle threshold; identifying a detection point based on the throttle threshold; and calculating a number of write/erase cycles based on the detection point and the throttle threshold for writing a memory device.

Abstract: An electronic device includes a subsystem, a plurality of energy storage elements coupled to the subsystem through one or more switches, and a charging and monitoring apparatus for concurrently charging the plurality of energy storage elements and monitoring operability of the energy storage elements. A first subset of the energy storage elements is coupled to a first node and a second subset of the energy storage elements is coupled to a second node of a bridge circuit. A power supply provides a DC charging voltage and an AC test voltage to both the first and second subsets of the energy storage elements. A monitoring circuit produces a predefined fault signal if a predefined electrical characteristic of the first subset of the energy storage elements differs from a same predefined electrical characteristic of the second subset of the energy storage elements by more than a predefined amount.

Abstract: The various embodiments described herein include methods and/or systems for throttling power in a storage device. In one aspect, a method of operation in a storage system includes obtaining a power metric corresponding to a count of active memory commands in the storage system, where active memory commands are commands being executed by the storage system. The method further includes, in accordance with a determination that the power metric satisfies one or more power thresholds, deferring execution of one or more pending memory commands.

Abstract: A method of operation in a non-volatile memory system for deferring, in accordance with a determination to reduce power consumption by the non-volatile memory system, execution of commands in a command queue corresponding to a distinct set of non-volatile memory devices during a respective wait period. In some implementations, the respective wait period for a first distinct set of non-volatile memory devices in at least two distinct sets is at least partially non-overlapping with the respective wait period for a second distinct set of non-volatile memory devices in the at least two distinct sets.

Abstract: A storage system, and a method of data hardening in the storage system, including: a de-glitch module configured for a detection of a power failure event; a write page module, coupled to the de-glitch module, the write page module configured for an execution of a cache write command based on the power failure event to send a cache page from a cache memory to a storage channel controller, wherein the cache memory is a volatile memory; and a signal empty module, coupled to the write page module, the signal empty module configured for a generation of a sleep signal to shut down a host bus adapter, wherein the host bus adapter interfaces with the storage channel controller to write the cache page back to the cache memory upon a power up of the host bus adapter and the storage channel controller.

Abstract: A system and method of data management with modular erase in a data storage system with a memory array having an erase block and a target block with the target block in a logical unit separate from the erase block including: performing an erase operation on the erase block, the erase operation having an operation matrix configured for partial erasing of the erase block; updating a command status for the erase block; enabling an intervening command on the target block based on the command status indicating an incomplete erase status with the intervening command updating the command status; performing an erase optimization based on the command status; performing an additional erase operation based on the erase optimization; and updating the command status to an erase complete status based on the additional erase operation.

Abstract: A system and method of operation of a data storage system includes: a memory die for determining a middle read threshold; a control unit, coupled to the memory die, for calculating a lower read threshold and an upper read threshold based on the middle read threshold and a memory element age; and a memory interface, coupled to the memory die, for reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation.

Abstract: A circuit, configured to detect faults in an array of data storage elements, comprises: a resistor network; a switching network for selectively coupling a specified portion of the resistor network to the array of data storage elements; a current monitoring module, where the current monitoring module is operable to monitor current flow through the specified portion of the resistor network; and a control module coupled to the switching network and the current monitoring module. The control module is operable to control the switching network, so as to couple the specified portion of the resistor network to the array of data storage elements, and to determine whether one or more predefined characteristics of the output of the current monitoring module meet predetermined fault criteria. The control module is further operable to initiate one or more remedial actions, when the one or more predefined characteristics meet the predetermined fault criteria.

Abstract: A method of fault testing in a storage device comprises testing, in accordance with a storage device testing protocol, operability of a plurality of distinct portions on the storage device. The testing includes, for each of the plurality of distinct portions on the storage device: performing one or more operations on a respective portion of the storage device; recording data corresponding to electrical current drawn during performance of the one or more operations on the respective portion of the storage device; analyzing the recorded data, including determining whether one or more predefined characteristics of the recorded data meets predetermined failure criteria; and, in accordance with a determination that the recorded data meets the predetermined failure criteria, performing one or more remedial actions including updating a mapping of the storage device to mark the respective portion as a known-bad portion.

Abstract: A method of fault detection includes, while in normal operation: recording data corresponding to measurements of electrical current drawn during performance of a respective operation on a specified portion of a storage device; analyzing the recorded data, including determining whether one or more predefined characteristics of the recorded data meets predetermined failure criteria; and in accordance with a determination that the recorded data meets the predetermined failure criteria, performing one or more remedial actions, the one or more remedial actions including marking the specified portion as a known-bad portion.

Abstract: Various embodiments described herein disclose systems, methods and/or devices used to dissipate heat generated by electronic components of an electronic assembly that further includes a first assembly rail, a top circuit board and a bottom circuit board. The first assembly rail includes a first card guide structure and a second card guide structure that are arranged on a first side of the first assembly rail near two opposite ends of the assembly rail. The top and the bottom circuit boards are mechanically coupled to the first and second card guide structures of the first assembly rail, respectively. The top circuit board is parallel to the bottom circuit board, and separated from the bottom circuit board by a predefined distance. The first assembly rail, the top circuit board and the bottom circuit board together form a channel there between for receiving a heat dissipating airflow.

Abstract: Various embodiments described herein include systems, methods and/or devices used to dissipate heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic assembly includes a first circuit board with one or more heat generating components coupled thereto. The electronic assembly further includes a second circuit board with one or more heat sensitive components coupled thereto. The electronic assembly also includes a thermal barrier interconnect. The thermal barrier interconnect electrically couples the first circuit board to the second circuit board. In some embodiments, thermal barrier interconnect is a flexible interconnect with a lower thermal conductivity than the first circuit board and the second circuit board. The thermal barrier interconnect forms a thermal barrier between the first and second circuit boards which protects the heat sensitive components from the heat generating components.

Abstract: Various embodiments described herein include systems, methods and/or devices for dissipating heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic assembly includes a first circuit board, a second circuit board flexibly coupled to the first circuit board, a connecting module coupled to the second circuit board, and a fastener. The fastener is configured to couple the first circuit board to the connecting module such that the first circuit board and the second circuit board are substantially parallel and are separated by a space, wherein the space forms at least part of a channel that is configured to direct airflow through the space between the first circuit board, second circuit board, and connecting module.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable dynamic brownout adjustment in a storage device. In one aspect, the method includes: (1) obtaining a set of power tolerance settings, the set of power tolerance settings used for determining whether one or more power supply voltages provided to the storage device are out of range, (2) in response to a predefined trigger, adjusting the set of power tolerance settings in accordance with one or more parameters of the storage device, (3) determining, in accordance with the adjusted set of power tolerance settings, whether the one or more power supply voltages are out of range, and (4) in accordance with a determination that the one or more power supply voltages are out of range, latching a power fail condition.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable firmware reversion triggering and control in a storage device. In one aspect, the method includes: (1) detecting a reversion trigger, the reversion trigger identifying a set of one or more controllers of a plurality of controllers on the storage device, and (2) in response to the reversion trigger, initiating recovery actions for each controller in the set of one or more controllers, including: for each controller in the set of one or more controllers: (a) asserting a revert signal to the controller to execute a firmware reversion for the controller, and (b) resetting the controller subsequent to asserting the revert signal to the controller.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, the method includes determining whether a power supply voltage provided to the storage device is higher than an over-voltage threshold. The method further includes, in accordance with a determination that the power supply voltage is higher than the over-voltage threshold, performing a power fail operation, the power fail operation including: (1) signaling a power fail condition to a plurality of controllers on the storage device, (2) transferring data held in volatile memory to non-volatile memory, and (3) removing power from the plurality of controllers on the storage device.