Patents by Inventor Rohit Bhatia

Rohit Bhatia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160253694
    Abstract: Systems and methods for generating human readable natural language summary for campaign audience are provided. The system includes a memory storing a database including audience segments and tags related to the audience segments. A computer server is in communication with the memory and the database, the computer server programmed to: obtain campaign delivery feed data related to a plurality of campaigns from at least one advertiser in a preset time period; obtain audience feed data including tag information from a data provider; cluster the tag information to find term frequencies for each term in the tag information; identify human understandable terms from the clustered tag information by removing noisy terms; and generate a human understandable report using the human understandable terms in a timely fashion.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Applicant: YAHOO! INC.
    Inventors: Zornitsa KOZAREVA, Lin MA, Rohit BHATIA
  • Publication number: 20160189204
    Abstract: Systems and methods for building keyword searchable audience based on performance ranking are provided. The system includes a processor and a non-transitory storage medium accessible to the processor. The system includes a memory storing a database comprising segment data and campaign data. A computer server is in communication with the memory and the database, the computer server programmed to: obtain a performance-lift vector for an audience segment; obtain a campaign vector using meta-data from the campaign data; obtain a keyword vector for the audience segment using the performance-lift vector and the campaign vector; receive an input from a user interface accessible to an advertiser; and search the segment data at least partially based on the input and the keyword vector for segments in the segment data.
    Type: Application
    Filed: December 31, 2014
    Publication date: June 30, 2016
    Applicant: Yahoo! Inc.
    Inventors: Lin MA, Rohit BHATIA, Xiao HAN
  • Patent number: 9348766
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Adi Basel, Gur Hildesheim, Shlomo Raikin, Robert Chappell, Ho-Seop Kim, Rohit Bhatia
  • Publication number: 20160127921
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to generate an overall performance index. The overall performance index is generated from data values from multiple different datasources that measure the same aspect of network performance of wireless providers of interest. The data values are used to generate metrics that measure the same aspect of network performance. The metrics are indexed and combined to generate an overall performance index.
    Type: Application
    Filed: April 30, 2015
    Publication date: May 5, 2016
    Inventors: Rohit Bhatia, Amilcar Pérez, Michael Greenawald, Kunal Barai, Joel Ullmann, Austin Albino
  • Publication number: 20160027048
    Abstract: Techniques are provided that include identifying and recommending one or more user segments as an audience for a particular campaign, such as an online advertising campaign, such as even if historical performance information for the particular campaign is limited or unavailable. Similar campaigns to the particular campaign may be identified. High-performing user segments for the similar campaigns may be identified. From these, one or more predicted best-performing user segments for the particular campaign may be identified and recommended as an audience for the particular campaign.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 28, 2016
    Applicant: YAHOO! INC.
    Inventors: Lin Ma, Rohit Bhatia, Xiao Han
  • Patent number: 9069690
    Abstract: In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Gur Hildesheim, Chang Kian Tan, Robert S. Chappell, Rohit Bhatia
  • Patent number: 9009630
    Abstract: A note-capture application is disclosed that allows notes to be displayed on the lock screen. In one embodiment, a note-capture application can be invoked when a mobile device is in an above-lock state. Note data can be captured using the note-capture application, and the captured data can be persistently displayed on the lock screen. A user can perform a unique gesture from the lock screen to invoke the note-capture application. In another embodiment, multiple input modes can be available for note data capture. For example, voice data, text data, camera data, etc. can all be used to capture notes for display on the lock screen.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: April 14, 2015
    Assignee: Microsoft Corporation
    Inventors: Michael J. Kruzeniski, Joseph B. Tobens, Jon Bell, William Scott Stauber, Rohit Bhatia, Ram Pattabhi Papatla, Daniel Escapa
  • Patent number: 8886979
    Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: November 11, 2014
    Assignee: Intel Corporation
    Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
  • Publication number: 20140215161
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways.
    Type: Application
    Filed: December 21, 2011
    Publication date: July 31, 2014
    Inventors: Adi Basel, Gur Hildeshem, Shlomo Raikin, Robert Chappell, Ho-Seop Kim, Rohit Bhatia
  • Publication number: 20140181484
    Abstract: According to one embodiment, a processor includes an execution pipeline for executing a plurality of threads, including a first thread and a second thread. The processor further includes a multi-thread controller (MTC) coupled to the execution pipeline to determine whether to switch threads between the first and second thread based on a thread switch policy that is selected from a list of thread switch policies based on unfairness levels of the first and second thread, and in response to determining to switch threads, to switch from executing the first thread to executing the second thread.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: James Callister, Don Soltis, Rohit Bhatia, Ramkumar Srinivasan, Steven Bostian, Richard M. Blumberg
  • Publication number: 20140075123
    Abstract: In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Inventors: Gur HILDESHEIM, Chang Kian TAN, Robert S. CHAPPELL, Rohit BHATIA
  • Publication number: 20140058919
    Abstract: An exemplary aspect comprises receiving data related to an underlying asset; calculating values corresponding to near-term implied volatility and realized volatility for the underlying asset; and transmitting data sufficient to describe an index based on a difference between the values corresponding to the near-term implied volatility and the realized volatility for the underlying asset. Another exemplary aspect comprises receiving electronic data related to an underlying asset; calculating data sufficient to describe a plurality of call options and a plurality of put options related to the underlying asset and written on a first settlement date; crediting an account with proceeds from selling the call and put options; and debiting the account to settle one or more of the options that are in-the-money on a second settlement date. Other aspects are apparent from the description and claims.
    Type: Application
    Filed: September 16, 2013
    Publication date: February 27, 2014
    Applicant: BARCLAYS CAPITAL INC.
    Inventors: Michael Schmanske, Maneesh Deshpande, Rohit Bhatia, Yidong Ding, Pankaj Khandelwal
  • Publication number: 20130326582
    Abstract: A note-capture application is disclosed that allows notes to be displayed on the lock screen. In one embodiment, a note-capture application can be invoked when a mobile device is in an above-lock state. Note data can be captured using the note-capture application, and the captured data can be persistently displayed on the lock screen. A user can perform a unique gesture from the lock screen to invoke the note-capture application. In another embodiment, multiple input modes can be available for note data capture. For example, voice data, text data, camera data, etc. can all be used to capture notes for display on the lock screen.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 5, 2013
    Applicant: Microsoft Corporation
    Inventors: Michael J. Kruzeniski, Joseph B. Tobens, Jon Bell, William Scott Stauber, Rohit Bhatia, Ram Pattabhi Papatla, Daniel Escapa
  • Publication number: 20130275787
    Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
    Type: Application
    Filed: June 10, 2013
    Publication date: October 17, 2013
    Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
  • Patent number: 8538849
    Abstract: An exemplary aspect comprises receiving data related to an underlying asset; calculating values corresponding to near-term implied volatility and realized volatility for the underlying asset; and transmitting data sufficient to describe an index based on a difference between the values corresponding to the near-term implied volatility and the realized volatility for the underlying asset. Another exemplary aspect comprises receiving electronic data related to an underlying asset; calculating data sufficient to describe a plurality of call options and a plurality of put options related to the underlying asset and written on a first settlement date; crediting an account with proceeds from selling the call and put options; and debiting the account to settle one or more of the options that are in-the-money on a second settlement date. Other aspects are apparent from the description and claims.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 17, 2013
    Assignee: Barclays Capital Inc.
    Inventors: Michael Schmanske, Maneesh Deshpande, Rohit Bhatia, Yidong Ding, Pankaj Khandelwal
  • Patent number: 8479029
    Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: July 2, 2013
    Assignee: Intel Corporation
    Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
  • Patent number: 8219780
    Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: July 10, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James R. Callister, Eric R. Delano, Rohit Bhatia, Shawn Kenneth Walker, Mark M. Gibson
  • Publication number: 20120023036
    Abstract: An exemplary aspect comprises receiving data related to an underlying asset; calculating values corresponding to near-term implied volatility and realized volatility for the underlying asset; and transmitting data sufficient to describe an index based on a difference between the values corresponding to the near-term implied volatility and the realized volatility for the underlying asset. Another exemplary aspect comprises receiving electronic data related to an underlying asset; calculating data sufficient to describe a plurality of call options and a plurality of put options related to the underlying asset and written on a first settlement date; crediting an account with proceeds from selling the call and put options; and debiting the account to settle one or more of the options that are in-the-money on a second settlement date. Other aspects are apparent from the description and claims.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 26, 2012
    Inventors: MICHAEL SCHMANSKE, Maneesh Deshpande, Rohit Bhatia, Yidong Ding, Pankaj Khandelwal
  • Publication number: 20110252255
    Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 13, 2011
    Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
  • Patent number: 7992017
    Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy