Abstract: In a computer system including a plurality of resources, techniques are disclosed for receiving a request from a software program to access a specified one of the plurality of resources, determining whether the specified one of the plurality of resources is a protected resource, and, if the specified one of the plurality of resources is a protected resource, for denying the request if the computer system is operating in a protected mode of operation, and processing the request based on access rights associated with the software program if the computer system is not operating in the protected mode of operation.

Abstract: Systems, methodologies, media, and other embodiments associated with activity factor based design are described. One exemplary system embodiment includes an activity factor logic configured to determine an activity factor for a first node. The activity factor relates an input activity for the first node to an output activity for the first node. The example system may also include a transmission factor logic configured to determine a transmission factor for the first node. The transmission factor describes a degree of causal power switching between the first node and a second node. The example system may also include a downstream power logic operably connected to the activity factor logic or the transmission factor logic. The downstream power logic may be configured to determine a power consumption amount for the second node. The power consumption amount may depend, for example, on the activity factor and the transmission factor.

Abstract: Methods and apparatus for stalling a pipeline, which methods and apparatus allow data in speed critical pipeline stages to propagate through additional stages of the pipeline. The data is then “caught” and stored in a deferred stall register as it is output from a downstream pipeline stage X. Finally, the data is output from the deferred stall register in a way that it masks the regular output of the pipeline stage X. In this manner, there is no need to store stalled data in a speed critical pipeline stage. Rather, the data can slip ahead, be saved, and be output at an appropriate time such that it appears that the data was stalled in the pipeline stage in which it existed at the time a stall was initiated.

Abstract: Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.

Abstract: The present invention relates to a system and method for establishing an illegal system state for a table which is preferably fully associative to disable matching of prospective entries (entries to be written to the table) with entries already resident in the table. Preferably, disabling the matching of prospective and table entries forces a system for updating the fully associative table or array to employ a pointer system for writing prospective entries into the fully associative table. The illegal system may be invoked automatically upon powering up the system for updating the fully associative array or may be associated with a machine specific state effected upon issuing a specific command during program execution.

Abstract: An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.

Abstract: The present invention relates to a mechanism for updating a fully associative array which is used to store entries associated with speculated instructions. Preferably, the array includes a plurality of data banks for storing entries, a plurality of ports for writing to the plurality of data banks, pointers associated with the respective banks for identifying table locations suitable for overwriting by upcoming entries, wherein an entry is suitable for overwriting when it is deemed invalid by the inventive system. A preferred embodiment is disclosed involving two ports writing to two banks wherein a plurality of factors is considered in deciding where prospective entries from the two ports will be written in the table. The Factors include, matches between existing and prospective entries, the default designated data bank for a given port, whether two write operations are being attempted simultaneously, and the number of entries already present in each data bank.

Abstract: A method and apparatus that utilizes a simple test and flush mechanism to implement branch instructions of one Instruction Set Architecture (ISA) using instructions of another ISA is described. During the decoding and sequencing of microinstructions to implement a branch instruction, a fix-up address, which represents the remedial branch target in the event of a mispredicted target or branch condition, is determined and stored. A test condition is set to determine if the prediction or the branch condition was correct. When the test condition fails, the instruction execution pipeline is immediately flushed to avoid executing any instruction remaining in the pipeline following the branch instructions. The flushing of the pipeline signals the instruction fetch control mechanism to redirect the instruction flow to the instruction corresponding to the fix-up address.

Abstract: The present invention relates to a system and method for establishing an illegal system state for a table which is preferably fully associative to disable matching of prospective entries (entries to be written to the table) with entries already resident in the table. Preferably, disabling the matching of prospective and table entries forces a system for updating the fully associative table or array to employ a pointer system for writing prospective entries into the fully associative table. The illegal system may be invoked automatically upon powering up the system for updating the fully associative array or may be associated with a machine specific state effected upon issuing a specific command during program execution.

Abstract: A system and method are disclosed which allow unstored computed results to be accessed without the normal overhead associated with traditional data forwarding and bypass techniques. Through the use of multiplexers and bi-directional OR controllers the unstored data is readily accessible for use before it is stored in a register file. The circuitry used also allows bi-directional travel across a register file or bank as information is passed between the bi-directional controllers used. Latches can also be used in the circuitry. Additionally, the features of the invention allow the required number of select signals fed to the multiplexers used to be reduced over conventional methods. These reductions are possible through circuitry disclosed herein.

Abstract: A system and method are disclosed which allow unstored computed results to be accessed without the normal overhead associated with traditional data forwarding and bypass techniques. Through the use of multiplexers and bi-directional OR controllers the unstored data is readily accessible for use before it is stored in a register file. The circuitry used also allows bi-directional travel across a register file or bank as information is passed between the bi directional controllers used. Latches can also be used in the circuitry. Additionally, the features of the invention allow the required number of select signals fed to the multiplexers used to be reduced over conventional methods. These reductions are possible through circuitry disclosed herein.

Abstract: The system is a method and an apparatus for resteering failing speculation check instructions in the pipeline of a processor. A branch offset immediate value and an instruction pointer correspond to each failing instruction. These values are used to determine the correct target recovery address. A relative adder adds the immediate value and the instruction pointer value to arrive at the target recovery address. This is done by flushing the pipeline upon the occurrence of a failing speculation check instruction. The pipeline flush is extended to allow the instruction stream to be resteered. The immediate value and the instruction pointer are then routed through the existing data paths of the pipeline, into the relative adder, which calculates the correct address. A sequencer tracks the progression of these values through the pipeline and causes a branch at the desired time.

Abstract: A processing unit of the invention has multiple instruction pipelines for processing multi-threaded instructions. Each thread may have an urgency associated with its program instructions. The processing unit has a thread switch controller to monitor processing of instructions through the various pipelines. The thread controller also controls switch events to move from one thread to another within the pipelines. The controller may modify the urgency of any thread such as by issuing an additional instruction. The thread controller preferably utilizes certain heuristics in making switch event decisions. A time slice expiration unit may also monitor expiration of threads for a given time slice.

Abstract: The present invention discloses a system and method for simultaneously identifying a most recent advanced load instruction employing a particular register and determining whether the instruction conflicts with a store instruction thereby requiring a recovery operation. Fully associative tables are advantageously employed for identifying the most recent load instruction, for comparing store instruction address information with addresses employed in advanced load instructions, and for logging a validity status associated with a register number. Parallel operation of load vs. check register numbers and load instruction and store instruction memory addresses conserves time and preferably enables a hit/miss determination for a particular check instruction to be completed in single machine cycle.

Abstract: The invention recasts the virtual register file frame calls to alias hazard detection in the hazard detect logic of the physical register file. By way of example, mapping to the stacked registers may be aliased with three sets of 32 registers rows, from 32 to 127, for data hazard calculations to decrease size implementation with minor performance decrease. The invention sacrifices occasional hazard detections—resulting in occasional pipeline stalls as a loss of processor performance—in order to remove the row-by-row dependencies on physical register size. The invention thus reduces the logic requirements associated with the “height” and “width” of the register file: “height” corresponds to the number of registers (e.g., 128), and “width” corresponds to the pipeline stages.

Abstract: A method and apparatus that generates a simplified, localized version (“a local stall”) of a global stall to improve the performance of a pipelined microprocessor. The local stall is generated when a data-dependency hazard is detected for a local consumer. Utilizing circuitry used in the pipelined microprocessor's data-forwarding circuitry, the local stall is generated with a relatively minor increase in circuitry. The local stall is generated much sooner than the global stall, arriving much sooner in a local pipeline. The local pipeline utilizes the local stall to override the global stall, when appropriate, and to ensure that correct data is read for a local consumer and to operate more efficiently than a standard pipeline without a local stall.

Abstract: A method and apparatus that utilizes a simplified, localized version (“a local data-dependency stall”) of a global data-dependency stall to avoid re-reading of a register file to improve the performance of a pipelined microprocessor. A non-asserted local data-dependency stall indicates that source operand for an instruction is correct. Accordingly, when a global data-dependency stall arrives, the instruction is stalled in a stage without re-reading the register file. Without the simplified, localized version of the global data-dependency stall, the source operand data is not known to be correct and is indeed assumed to be incorrect. Therefore, when the global data-dependency stall arrives, a complete re-computation of the source operand data must be performed, including a re-read of the register file. Likewise, an asserted local data-dependency stall indicates that source operand for an instruction is not correct.

Abstract: A Quasi Radix-16 Butterfly comprises an radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfly processor for application as data inputs to the radix-4 butterfly processor in a second series of butterfly operations to implement high-speed processing that is maximally execution-bound.