Patents by Inventor Roland Rupp

Roland Rupp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11139375
    Abstract: According to an embodiment of a method described herein, a silicon carbide substrate is provided that includes a plurality of device regions. A front side metallization may be provided at a front side of the silicon carbide substrate. The method may further comprise providing an auxiliary structure at a backside of the silicon carbide substrate. The auxiliary structure includes a plurality of laterally separated metal portions. Each metal portion is in contact with one device region of the plurality of device regions.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 5, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Carsten Schaeffer, Alexander Breymesser, Bernhard Goller, Ronny Kern, Matteo Piccin, Roland Rupp, Francisco Javier Santos Rodriguez
  • Publication number: 20210305198
    Abstract: A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 30, 2021
    Inventors: Carsten von Koblinski, Daniel Pedone, Matteo Piccin, Roland Rupp, Chiew Li Tai, Jia Yi Wong
  • Publication number: 20210290582
    Abstract: The present invention relates to pharmaceutical compositions containing dimethyl fumarate (DMF), More specifically, the present invention relates to a pharmaceutical composition for oral use in treating hyperproliferative, inflammatory or autoimmune disorders by administering a low daily dosage in the range of 410 mg±5% or 400 mg±5% dimethyl fumarate, wherein the pharmaceutical formulation is in the form of an erosion matrix tablet.
    Type: Application
    Filed: October 26, 2020
    Publication date: September 23, 2021
    Inventors: Christin Galetzka, Chris Rundfeldt, Roland Rupp, Peder M. Andersen
  • Patent number: 11121220
    Abstract: A semiconductor device includes a silicon carbide semiconductor body including a source region of a first conductivity type, a body region of a second conductivity type, shielding regions of the second conductivity type and compensation regions of the second conductivity type. Trench structures extend from a first surface into the silicon carbide semiconductor body along a vertical direction. Each of the trench structures includes an auxiliary electrode at a bottom of the trench structure and a gate electrode between the auxiliary electrode and the first surface. The auxiliary electrode is electrically insulated from the gate electrode. The auxiliary electrode of each of the trench structures is adjoined by at least one of the shielding regions at the bottom of the trench structure. Each of the shielding regions is adjoined by at least one of the compensation regions at the bottom of the shielding region.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: September 14, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder, Roland Rupp
  • Patent number: 11107893
    Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 500/cm2. An acceptor layer is attached at the graphene layer to form a wafer-stack. The acceptor layer includes silicon carbide having a second defect density higher than first defect density. The wafer-stack is split along a split plane in the silicon carbide substrate to form a device wafer including the graphene layer and a silicon carbide split layer at the graphene layer. An epitaxial silicon carbide layer extending to an upper side of the device wafer is formed on the silicon carbide split layer. The device wafer is further processed at the upper side.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 31, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp
  • Patent number: 11107732
    Abstract: A method for processing a wide band gap semiconductor wafer is proposed. The method includes depositing a non-monocrystalline support layer at a back side of a wide band gap semiconductor wafer, depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer, and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer including at least a part of the epitaxial layer, and a remaining wafer including the non-monocrystalline support layer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: August 31, 2021
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Guenter Denifl, Tobias Franz Wolfgang Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
  • Publication number: 20210265484
    Abstract: A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Inventors: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
  • Patent number: 11069778
    Abstract: A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Ronny Kern
  • Patent number: 11063144
    Abstract: A semiconductor component includes a SiC semiconductor body. A drift zone of a first conductivity type and a semiconductor region are formed in the SiC semiconductor body. Barrier structures extending from the semiconductor region into the drift zone differ from the gate structures.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: July 13, 2021
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Larissa Wehrhahn-Kilian, Bernd Zippelius
  • Patent number: 11046577
    Abstract: In various embodiments, a method of processing a monocrystalline substrate is provided. The method may include severing the substrate along a main processing side into at least two monocrystalline substrate segments, and forming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: June 29, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andre Brockmeier, Roland Rupp, Francisco Javier Santos Rodriguez
  • Patent number: 11031483
    Abstract: A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 8, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
  • Publication number: 20210167203
    Abstract: A method of manufacturing semiconductor devices includes: forming source regions of a first conductivity type in a SiC-based semiconductor substrate, wherein dopants are introduced selectively through first segments of first mask openings in a first dopant mask and wherein a longitudinal axis of the first mask opening extends into a first horizontal direction; forming pinning regions of a complementary second conductivity type, wherein dopants are selectively introduced through second segments of the first mask openings and wherein the first and second segments alternate along the first horizontal direction; and forming body regions of the second conductivity type, wherein dopants are selectively introduced through second mask openings in a second dopant mask, wherein a width of the second mask openings along a second horizontal direction orthogonal to the first horizontal direction is greater than a width of the first mask openings.
    Type: Application
    Filed: February 10, 2021
    Publication date: June 3, 2021
    Inventors: Andreas Peter Meiser, Romain Esteve, Roland Rupp
  • Patent number: 10967450
    Abstract: A method of yielding a thinner product wafer from a thicker base SiC wafer cut from a SiC ingot includes: supporting the base SiC wafer with a support substrate: and while the base SiC wafer is supported by the support substrate, cutting through the base SiC wafer in a direction parallel to a first main surface of the base SiC wafer using a wire as part of a wire electrical discharge machining (WEDM) process, to separate the product wafer from the base SiC wafer, the product wafer being attached to the support substrate when cut from the base SiC wafer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Nirdesh Ojha, Francisco Javier Santos Rodriguez, Roland Rupp, Markus Heinrici, Karin Delalut, Claudia Friza
  • Patent number: 10964808
    Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a semiconductor body of silicon carbide. The trench gate structures include a gate electrode and are spaced apart from one another along a first horizontal direction and extend into a body region with a longitudinal axis parallel to the first horizontal direction. First sections of first pn junctions between the body regions and a drift structure are tilted to the first surface and parallel to the first horizontal direction. Source regions form second pn junctions with the body regions. A gate length of the gate electrode along a second horizontal direction orthogonal to the first horizontal direction is greater than a channel length between the first sections of the first pn junctions and the second pn junctions.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 30, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Romain Esteve, Roland Rupp
  • Publication number: 20210053148
    Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 25, 2021
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko Swoboda
  • Patent number: 10915029
    Abstract: A semiconductor device is provided that includes a silicon carbide substrate including a main surface at which a plurality of doped zones are formed in a junction termination extension zone of the silicon carbide substrate, the plurality of doped zones are arranged such that a lateral dopant concentration gradient is formed that decreases from a central region of the silicon carbide substrate to an outer edge region of the silicon carbide substrate.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: February 9, 2021
    Inventors: Roland Rupp, Rudolf Elpelt, Romain Esteve
  • Patent number: 10903078
    Abstract: A method for processing a silicon carbide wafer includes implanting ions into the silicon carbide wafer to form an absorption layer in the silicon carbide wafer. The absorption coefficient of the absorption layer is at least 100 times the absorption coefficient of silicon carbide material of the silicon carbide wafer outside the absorption layer, for light of a target wavelength. The silicon carbide wafer is split along the absorption layer at least by irradiating the silicon carbide wafer with light of the target wavelength to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Guenter Denifl, Mihai Draghici, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Wolfgang Lehnert, Roland Rupp, Werner Schustereder
  • Patent number: 10861964
    Abstract: A semiconductor device includes a drift zone formed in a semiconductor portion. In a transition section of the semiconductor portion a vertical extension of the semiconductor portion decreases from a first vertical extension to a second vertical extension. A junction termination zone of a conductivity type complementary to a conductivity type of the drift zone is formed between a first surface of the semiconductor portion and the drift zone and includes a tapering portion in the transition section. In the tapering portion a vertical extension of the junction termination zone decreases from a maximum vertical extension to zero within a lateral width of at least twice the maximum vertical extension.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: December 8, 2020
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Rudolf Elpelt, Reinhold Schoerner, Larissa Wehrhahn-Kilian, Bernd Zippelius
  • Publication number: 20200381256
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 3, 2020
    Inventors: Francisco Javier SANTOS RODRIGUEZ, Roland RUPP, Hans-Joachim SCHULZE
  • Publication number: 20200365754
    Abstract: A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze