Abstract: A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.

Abstract: The accuracy of electronic design automation is increased by determining whether fill wires in a putative integrated circuit design should be effectively grounded or floating. For each signal wire in the putative design adjacent to the fill wires, a signal sensitivity value, which represents sensitivity of a given one of the plurality of signal wires to noise and timing, is determined. For each one of the fill wires, a fill sensitivity value is determined by: identifying coupling of each one of the fill wires to the adjacent signal wires; and calculating the fill sensitivity value as a combination of the signal sensitivity values of each of the adjacent signal wires for which the coupling has been identified. At least a portion of the fill wires are selectively effectively grounded based on the fill sensitivity value, to obtain a modified design.

Abstract: The accuracy of electronic design automation is increased by determining whether fill wires in a putative integrated circuit design should be effectively grounded or floating. For each signal wire in the putative design adjacent to the fill wires, a signal sensitivity value, which represents sensitivity of a given one of the plurality of signal wires to noise and timing, is determined. For each one of the fill wires, a fill sensitivity value is determined by: identifying coupling of each one of the fill wires to the adjacent signal wires; and calculating the fill sensitivity value as a combination of the signal sensitivity values of each of the adjacent signal wires for which the coupling has been identified. At least a portion of the fill wires are selectively effectively grounded based on the fill sensitivity value, to obtain a modified design.

Abstract: A system and method to perform capacitance extraction involves defining a location of signal wires and floating metal of an integrated circuit design. The method includes designating one of the signal wires as a target wire, defining a first area within which first capacitances between the target wire and the floating metal and other signal wires are determined, defining a second area, within which second capacitances between floating metal within the first area and the floating metal and the other signal wires not within the first area are determined, and generating an intermediate capacitive network. The intermediate capacitive network includes the target wire, the floating metal, and the other signal wires within the second area, the first capacitances and the second capacitances. A capacitive network is generated from the intermediate capacitive network. The first capacitances and the second capacitances are used to generate third capacitance values of the capacitive network.

Abstract: A system and method to perform capacitance extraction involves defining a location of signal wires and floating metal of an integrated circuit design. The method includes designating one of the signal wires as a target wire, defining a first area within which first capacitances between the target wire and the floating metal and other signal wires are determined, defining a second area, within which second capacitances between floating metal within the first area and the floating metal and the other signal wires not within the first area are determined, and generating an intermediate capacitive network. The intermediate capacitive network includes the target wire, the floating metal, and the other signal wires within the second area, the first capacitances and the second capacitances. A capacitive network is generated from the intermediate capacitive network. The first capacitances and the second capacitances are used to generate third capacitance values of the capacitive network.

Abstract: A method for predicting noise propagation in a circuit comprising correlating noise results predicted by a circuit model to a transistor level model with a processor, generating a first best fit data analytics model for identifying the optimal output pin capacitance as a function of circuit conditions and store the first best fit model in a noise rule file in a memory, generating a second best fit data analytics model for predicting noise peak output from the circuit model as a function of the circuit conditions and store the second best fit model in the noise rule file in the memory, and applying the first best fit model and the second best fit model in a noise analysis simulation to identify and simulate an optimal circuit.

Abstract: A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.

Abstract: A system for semiconductor chip fabrication. A host system hosts a capacitance adjust tool for performing calculating a ground capacitance adjust for a wire segment going through routing tiles according to the following operations; providing the routing tiles having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires; computing ground capacitance adjusts for a victim wire averaged across all aggressor slew values and across possible spacing values between the victim wire and the neighboring aggressor wires to take into account a potential coupling effect by the neighboring aggressor wires, to guide placement of the wire segment in the routing tiles to avoid coupling noise; and outputting the placement of the wire segments to a tool for manufacturing the semiconductor chip.

Abstract: A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.

Abstract: A system for semiconductor chip fabrication. A host system hosts a capacitance adjust tool for performing calculating a ground capacitance adjust for a wire segment going through routing tiles according to the following operations; providing the routing tiles having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires; computing ground capacitance adjusts for a victim wire averaged across all aggressor slew values and across possible spacing values between the victim wire and the neighboring aggressor wires to take into account a potential coupling effect by the neighboring aggressor wires, to guide placement of the wire segment in the routing tiles to avoid coupling noise; and outputting the placement of the wire segments to a tool for manufacturing the semiconductor chip.

Abstract: A computer implemented method for calculating a ground capacitance adjust for a wire segment going through a given routing tile. The method includes providing the routing tile having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires; computing ground capacitance adjusts for a victim wire averaged across all aggressor slew values and across possible spacing values between the victim wire and the neighboring aggressor wires to take into account a potential coupling effect by the neighboring aggressor wires, assuming a distribution of signal slews of wires belonging to the routing tile and assuming the victim wire's neighbors have signal slews from the distribution of slews for this tile for possible spacing values responsible for the coupling effect, to guide placement of the wire segment in the routing tile to avoid coupling noise.

Abstract: A method for predicting noise propagation in a circuit comprising correlating noise results predicted by a circuit model to a transistor level model with a processor, generating a first best fit data analytics model for identifying the optimal output pin capacitance as a function of circuit conditions and store the first best fit model in a noise rule file in a memory, generating a second best fit data analytics model for predicting noise peak output from the circuit model as a function of the circuit conditions and store the second best fit model in the noise rule file in the memory, and applying the first best fit model and the second best fit model in a noise analysis simulation to identify and simulate an optimal circuit.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: A method for predicting noise propagation in a circuit comprising correlating noise results predicted by a circuit model to a transistor level model with a processor, generating a first best fit data analytics model for identifying the optimal output pin capacitance as a function of circuit conditions and store the first best fit model in a noise rule file in a memory, generating a second best fit data analytics model for predicting noise peak output from the circuit model as a function of the circuit conditions and store the second best fit model in the noise rule file in the memory, and applying the first best fit model and the second best fit model in a noise analysis simulation to identify and simulate an optimal circuit.

Abstract: Embodiments include methods, processing systems and computer program products for extracting via capacitance. Aspects include placing various shapes of target nets of an IC into a Cshapes collection and a CshapesVia collection, processing the shapes in these collections and placing the processed shapes into a Ctile collection and a CtilesVia collection, and extracting via capacitance of the target nets through each of Cshapes, CshapesVia, Ctiles, and CtilesVia collections. In exemplary embodiments, the processing operation includes: reducing the complexity of the shapes in the shape collections, removing all overhang shapes, and all overlapped shapes from the shape collections, and unioning the shapes in the Cshapes collection and the CshapesVia collection, respectively.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: A method may include: specifying a random nets credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; identifying all nets including fan-in and fan-out cones connected to each net that exceeds the upper bound and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all identified nets, to adjust the initial IC design, to close timing and generate a final IC design.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.