Abstract: A method may include: specifying a random nets credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; identifying all nets including fan-in and fan-out cones connected to each net that exceeds the upper bound and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all identified nets, to adjust the initial IC design, to close timing and generate a final IC design.

Abstract: A computer implemented method for calculating a ground capacitance adjust for a wire segment going through a given routing tile. The method includes providing the routing tile having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires; computing ground capacitance adjusts for a victim wire averaged across all aggressor slew values and across possible spacing values between the victim wire and the neighboring aggressor wires to take into account a potential coupling effect by the neighboring aggressor wires, assuming a distribution of signal slews of wires belonging to the routing tile and assuming the victim wire's neighbors have signal slews from the distribution of slews for this tile for possible spacing values responsible for the coupling effect, to guide placement of the wire segment in the routing tile to avoid coupling noise.

Abstract: Aspects of the present invention include a method, system and computer program product. The method includes identifying an overall shape as part of a design of circuitry of an integrated circuit or a semiconductor chip, and partitioning the overall shape into a plurality of sub-shapes. The method also includes performing a capacitance extraction for each sub-shape, each sub-shape including the sub-shape itself and at least one portion of at least one adjacent sub-shape, wherein the performing a capacitance extraction determines an amount of capacitance for each sub-shape. The method further includes combining the determined amount of capacitance for each sub-shape into a total determined amount of capacitance for the overall shape.

Abstract: A method for predicting noise propagation in a circuit comprising correlating noise results predicted by a circuit model to a transistor level model with a processor, generating a first best fit data analytics model for identifying the optimal output pin capacitance as a function of circuit conditions and store the first best fit model in a noise rule file in a memory, generating a second best fit data analytics model for predicting noise peak output from the circuit model as a function of the circuit conditions and store the second best fit model in the noise rule file in the memory, and applying the first best fit model and the second best fit model in a noise analysis simulation to identify and simulate an optimal circuit.

Abstract: Embodiments include methods, processing systems and computer program products for extracting via capacitance. Aspects include placing various shapes of target nets of an IC into a Cshapes collection and a CshapesVia collection, processing the shapes in these collections and placing the processed shapes into a Ctile collection and a CtilesVia collection, and extracting via capacitance of the target nets through each of Cshapes, CshapesVia, Ctiles, and CtilesVia collections. In exemplary embodiments, the processing operation includes: reducing the complexity of the shapes in the shape collections, removing all overhang shapes, and all overlapped shapes from the shape collections, and unioning the shapes in the Cshapes collection and the CshapesVia collection, respectively.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.

Abstract: A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: A method may include: specifying a random noise credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; performing an initial noise-free timing analysis of the IC design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; marking all nets, including fan-in and fan-out cones, connected to each net that exceeds the upper bound; and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all marked nets, to adjust the initial IC design, to close timing and generate a final IC design.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: A method and system to route connections of sub-networks in a design of an integrated circuit and a computer program product are described. The system includes a memory device to store instructions to route the connections of the sub-networks, and a processor to execute the instructions to determine a baseline route for each of the connections of each of the sub-networks, identify noise critical sub-networks in the integrated circuit design based on congestion, set a mean threshold length (MTL), segment the connections of the noise critical sub-networks based on the MTL, and re-route the baseline route based on segmenting. The MTL indicates a maximum length of each segment of each connection, each segment includes a different wirecode which is different from a wirecode of an adjacent segment, and each wirecode defines a width, a metal layer, and a spacing for each segment.

Abstract: A method and system to route connections of sub-networks in a design of an integrated circuit and a computer program product are described. The method includes determining a baseline route for each of the connections of each of the sub-networks, identifying noise critical sub-networks in the design of the integrated circuit based on congestion, and setting a mean threshold length (MTL), the MTL indicating a maximum length of each segment of each connection. Each segment includes a wirecode which is different from a wirecode of an adjacent segment, each wirecode defining a width, a metal layer, and a spacing for each segment. The method also includes segmenting the connections of the noise critical sub-networks based on the MTL, and re-routing the baseline route based on the segmenting.

Abstract: A method and system to route connections of sub-networks in a design block of an integrated circuit and a computer program product are described. The system includes a memory device to store instructions to route the connections of the sub-networks, and a processor to execute the instructions to determine a baseline route for each of the connections of each of the sub-networks, identify noise critical sub-networks in the integrated circuit design based on congestion, set a mean threshold length (MTL), segment the connections of the noise critical sub-networks based on the MTL, and re-route the baseline route based on segmenting. The MTL indicates a maximum length of each segment of each connection, each segment includes a different wirecode than an adjacent segment, and the wirecode defines a width, metal layer, and spacing for the segment.

Abstract: A method and system to route connections of sub-networks in a design of an integrated circuit and a computer program product are described. The method includes determining a baseline route for each of the connections of each of the sub-networks, identifying noise critical sub-networks in the design of the integrated circuit based on congestion, and setting a mean threshold length (MTL), the MTL indicating a maximum length of each segment of each connection. Each segment includes a wirecode which is different from a wirecode of an adjacent segment, each wirecode defining a width, a metal layer, and a spacing for each segment. The method also includes segmenting the connections of the noise critical sub-networks based on the MTL, and re-routing the baseline route based on the segmenting.

Abstract: A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.