Patents by Inventor Ronald D. Rose
Ronald D. Rose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8655634Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.Type: GrantFiled: March 10, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: David J. Hathaway, Vasant Rao, Ronald D. Rose, Ali Sadigh, Jeffrey P. Soreff, David W. Winston
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Patent number: 8645899Abstract: The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.Type: GrantFiled: March 31, 2009Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: David J. Widiger, Ronald D. Rose, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb
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Patent number: 8640062Abstract: A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.Type: GrantFiled: June 10, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Kanak B. Agarwal, Sani R. Nassif, Ronald D. Rose, Chenggang Xu
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Patent number: 8612918Abstract: The present disclosure is directed to a method for extracting information for a circuit design. The method includes establishing a reflexive relationship between a plurality of design shapes corresponding to a plurality of circuit components in the circuit design. The method includes receiving a design change for at least one design shape of the plurality of design shapes. The method includes identifying a set of changed shapes, a set of affected shapes, and a set of involved shapes. The method includes extracting at least one of a capacitance, an inductance or a resistance for the updated circuit design based on at least one of the set of changed shapes, the set of affected shapes and the set of involved shapes. The method includes updating the plurality of circuit components in the circuit design based on at least one of the set of changed shapes and the set of affected shapes.Type: GrantFiled: March 22, 2012Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: David J. Widiger, Ronald D. Rose, Sandy K Kao, Lewis W Dewey, III, Gerald F Plumb
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Patent number: 8539428Abstract: The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.Type: GrantFiled: March 22, 2012Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: David J. Widiger, Ronald D. Rose, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb
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Patent number: 8438001Abstract: Method and apparatus for improving performance of noise analysis using a threshold based combination of noise estimation and simulation. The method includes classifying a circuit into one of four defined groups, determining if an input noise is small enough to skip simulation, estimating an output noise wave, scaling down a generated wave by a scaling factor depending on the circuit type, and determining if the estimated output noise is small enough to propagate or instead requires simulation.Type: GrantFiled: May 7, 2008Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Anita Natarajan, Ronald D. Rose, Sanjay Upreti
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Publication number: 20120317529Abstract: A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: International Business Machines CorporationInventors: Kanak B. Agarwal, Sani R. Nassif, Ronald D. Rose, Chenggang Xu
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Publication number: 20120185815Abstract: The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.Type: ApplicationFiled: March 22, 2012Publication date: July 19, 2012Applicant: International Business Machines CorporationInventors: David J. Widiger, Ronald D. Rose, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb
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Publication number: 20120180013Abstract: The present disclosure is directed to a method for extracting information for a circuit design. The method includes establishing a reflexive relationship between a plurality of design shapes corresponding to a plurality of circuit components in the circuit design. The method includes receiving a design change for at least one design shape of the plurality of design shapes. The method includes identifying a set of changed shapes, a set of affected shapes, and a set of involved shapes. The method includes extracting at least one of a capacitance, an inductance or a resistance for the updated circuit design based on at least one of the set of changed shapes, the set of affected shapes and the set of involved shapes. The method includes updating the plurality of circuit components in the circuit design based on at least one of the set of changed shapes and the set of affected shapes.Type: ApplicationFiled: March 22, 2012Publication date: July 12, 2012Applicant: International Business Machines CorporationInventors: David J. Widiger, Ronald D. Rose, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb
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Publication number: 20110224965Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.Type: ApplicationFiled: March 10, 2010Publication date: September 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David J. Hathaway, Vasant Rao, Ronald D. Rose, Ali Sadigh, Jeffrey P. Soreff, David W. Winston
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Publication number: 20110088008Abstract: A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.Type: ApplicationFiled: October 14, 2009Publication date: April 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. FIFIELD, Mark C. HAKEY, Jason D. HIBBELER, James S. NAKOS, Tak H. NING, Kenneth P. RODBELL, Ronald D. ROSE, Henry H.K. TANG, Larry WISSEL
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Publication number: 20100251198Abstract: The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David J. Widiger, Ronald D. Rose, Sandy K. Kao, Lewis W. Dewey, III, Gerald F. Plumb
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Publication number: 20090281781Abstract: A method, apparatus and program product are provided for performing a noise, timing, or other signal integrity simulation of a circuit under test. A simulation cache structure is accessed to retrieve cached simulation results for a first portion of the circuit under test. Simulation is performed on a second portion of the circuit under test to generate simulation results for the second portion. Simulation results are generated for the circuit under test by combining the simulation results for the second portion with the cached simulation results for the first portion.Type: ApplicationFiled: May 6, 2008Publication date: November 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald D. Rose, Sanjay Upreti
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Publication number: 20090281750Abstract: Method and apparatus for improving performance of noise analysis using a threshold based combination of noise estimation and simulation. The method includes classifying a circuit into one of four defined groups, determining if an input noise is small enough to skip simulation, estimating an output noise wave, scaling down a generated wave by a scaling factor depending on the circuit type, and determining if the estimated output noise is small enough to propagate or instead requires simulation.Type: ApplicationFiled: May 7, 2008Publication date: November 12, 2009Inventors: Anita Natarajan, Ronald D. Rose, Sanjay Upreti
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Patent number: 7127689Abstract: A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source for a static noise analysis of the circuit.Type: GrantFiled: May 28, 2004Date of Patent: October 24, 2006Assignee: International Business Machines CorporationInventors: Paul D. Kartschoke, Thomas G. Mitchell, Norman J. Rohrer, Ronald D. Rose
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Patent number: 7089513Abstract: A method, system and program product for designing an integrated circuit (IC) for signal integrity. The invention conducts a signal integrity analysis on an IC design; identifies any field effect transistor (FET) that causes a signal integrity failure in the case that the IC design fails the signal integrity analysis; and modifies an edge of a failing FET that is closer than a threshold distance to a well edge. The invention eliminates the manual, iterative procedure for determining the device causing a signal integrity failure due to well proximity effects.Type: GrantFiled: March 19, 2004Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: Karen A. Bard, Ronald D. Rose, Michael H. Sitko
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Publication number: 20030188267Abstract: A circuit model and method for modeling circuit waveforms. The elements present in the basic model are capacitors and ideal current sources. The adaptability and accuracy of the model is made possible by explicitly tabulating all element values as simultaneous functions of all input and output voltages, and using a high-dimensional interpolation technique of arbitrary order. The topology chosen is the simplest one that still shows the necessary qualitative features and allows for simple generalization to multiple input/output pins. Accuracy is also provided by the implicit nature of the ordinary differential equation (ODE) used to solve for the output voltages.Type: ApplicationFiled: March 29, 2002Publication date: October 2, 2003Applicant: International Business Machines CorporationInventors: Timothy S. Lehner, Khalid Rahmat, Ronald D. Rose, Rouwaida Kanj
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Patent number: 6567773Abstract: A method and structure for analyzing the effect of electrical noise in an integrated circuit fabricated in a silicon-on-insulator (“SOI”) technology. The present invention uses a static noise analysis to evaluate an integrated circuit's response to electrical noise, taking into account hysteresis effect and parasitic bipolar current voltage, both of which are unique to integrated circuits fabricated in a SOI technology process. The present invention also includes a computer, computer storage device, computer program and software incorporating the method steps and simulating the testing and analysis of the circuit under test.Type: GrantFiled: November 17, 1999Date of Patent: May 20, 2003Assignee: International Business Machines CorporationInventors: Khalid Rahmat, Ronald D. Rose