Patents by Inventor Ronald H. Sartore
Ronald H. Sartore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10241702Abstract: A sequential delay mechanism is provided for a memory subsystem of a host system. A first independent SAVE region of NVDIMMs of the memory subsystem is configured to start a memory SAVE immediately upon receiving a SAVE signal from the host system, and other independent SAVE regions of the NVDIMMs are configured to implement the delay mechanism. A memory SAVE to the NVDIMMs is activated immediately in the first independent SAVE region when the SAVE signal is received, and the other independent SAVE regions sequentially delay their activation of the memory SAVE.Type: GrantFiled: September 29, 2017Date of Patent: March 26, 2019Assignee: AgigA Tech Inc.Inventors: Ronald H Sartore, Torry J Steed
-
Patent number: 10216685Abstract: A memory module is organized into slice sections, each configured to input and output a slice of data for a different section of a data bus. Each slice section includes at least one nonvolatile memory (NVM) and a memory element, such as random access volatile memory, to store the slice of data for the slice section during operations that transfer the slice of data between the section of the data bus for the slice section and the NVM of the slice section. Each slice section also includes a slice controller configured to translate an address for the slice of data for the section of the data bus into a physical address of the NVM of the slice section.Type: GrantFiled: December 7, 2017Date of Patent: February 26, 2019Assignee: AgigA Tech Inc.Inventors: Ronald H Sartore, Thomas O. Koger
-
Patent number: 10134451Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.Type: GrantFiled: October 17, 2017Date of Patent: November 20, 2018Assignee: AgigA Tech IncInventors: Ronald H. Sartore, Yingnan Liu, Lane Hauck
-
Patent number: 9842628Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.Type: GrantFiled: July 10, 2008Date of Patent: December 12, 2017Assignee: AGIGA TECH INC.Inventors: Ronald H Sartore, Yingnan Liu, Lane Hauck
-
Publication number: 20170235404Abstract: An apparatus and method for providing an active feedback of a position of a conductive object, manipulated by a user on a sensing device, to allow detection of a reference location on the sensing device by the user. The apparatus may include a sensing device to detect a presence of a conductive object, manipulated by a user on the sensing device, a processing device coupled to the sensing device, the processing device to determine a position of the conductive object on the sensing device, and a feedback mechanism coupled to the processing device to provide an active feedback to the user to allow detection of a reference location on the sensing device by the user.Type: ApplicationFiled: February 17, 2016Publication date: August 17, 2017Inventors: Edward L. Grivna, David G. Wright, Ronald H. Sartore
-
Patent number: 9292091Abstract: An apparatus and method for providing an active feedback of a position of a conductive object, manipulated by a user on a sensing device, to allow detection of a reference location on the sensing device by the user. The apparatus may include a sensing device to detect a presence of a conductive object, manipulated by a user on the sensing device, a processing device coupled to the sensing device, the processing device to determine a position of the conductive object on the sensing device, and a feedback mechanism coupled to the processing device to provide an active feedback to the user to allow detection of a reference location on the sensing device by the user.Type: GrantFiled: September 17, 2013Date of Patent: March 22, 2016Assignee: Cypress Semiconductor CorporationInventors: Edward L. Grivna, David G. Wright, Ronald H. Sartore
-
Patent number: 9244836Abstract: A memory system distributes across multiple pages of a flash memory bits of a DRAM data word, the data word having a number of bits equal to a width of a row of a DRAM memory, and the bits of the data word all from a same row of the DRAM memory.Type: GrantFiled: November 23, 2009Date of Patent: January 26, 2016Assignee: AgigA Tech Inc.Inventor: Ronald H. Sartore
-
Patent number: 9164848Abstract: A memory module includes a volatile memory, a non-volatile memory, and a memory controller adapted to present to a host system external to the memory module an address space that includes an address space of the volatile memory and excludes all addresses of the non-volatile memory capacity. The module includes logic to copy the contents of the volatile memory to memory locations of the nonvolatile memory capacity reserved for backup of the volatile memory, using power from a backup power interface, when suitable power from the host system is unavailable, wherein the memory controller reserves for backup of the volatile memory an amount of nonvolatile memory storage capacity that is at least twice a memory storage capacity of the volatile memory.Type: GrantFiled: June 9, 2014Date of Patent: October 20, 2015Assignee: AgigA Tech IncInventor: Ronald H Sartore
-
Patent number: 9013946Abstract: A memory module includes volatile memory and non-volatile memory. The module includes logic to check if a non-volatile memory comprises un-erased areas, and if the non-volatile memory comprises un-erased areas, to elevate a backup capacitor potential above a predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory. The module includes logic to ERASE the un-erased areas and to return the capacitor to the predetermined operating potential after the ERASE is complete.Type: GrantFiled: January 14, 2013Date of Patent: April 21, 2015Assignee: AgigA Tech Inc.Inventor: Ronald H. Sartore
-
Publication number: 20140359237Abstract: “A memory module includes a volatile memory, a non-volatile memory, and a memory controller adapted to present to a host system external to the memory module an address space that includes an address space of the volatile memory and excludes all addresses of the non-volatile memory capacity. The module includes logic to copy the contents of the volatile memory to memory locations of the nonvolatile memory capacity reserved for backup of the volatile memory, using power from a backup power interface, when suitable power from the host system is unavailable, wherein the memory controller reserves for backup of the volatile memory an amount of nonvolatile memory storage capacity that is at least twice a memory storage capacity of the volatile memory.Type: ApplicationFiled: June 9, 2014Publication date: December 4, 2014Inventor: Ronald H. Sartore
-
Patent number: 8819368Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.Type: GrantFiled: May 28, 2012Date of Patent: August 26, 2014Assignee: AgigA Tech Inc.Inventor: Ronald H Sartore
-
Patent number: 8812802Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.Type: GrantFiled: May 28, 2012Date of Patent: August 19, 2014Assignee: AgigA Tech, Inc.Inventor: Ronald H Sartore
-
Patent number: 8650363Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.Type: GrantFiled: May 27, 2012Date of Patent: February 11, 2014Assignee: AgigA TechInventor: Ronald H Sartore
-
Patent number: 8537119Abstract: Devices including an audio mechanism and a processing device coupled to display on-screen buttons on a touch-screen display are described. The processing device is configured to detect a conductive object proximate to the touch-screen display and to determine a position of the conductive object on the touch-screen display. The processing device is configured to provide different sounds via the audio mechanism for different ones of the on-screen buttons when the position of the conductive object is determined within the different on-screen buttons to allow detection of a reference location on the touch-screen display.Type: GrantFiled: February 21, 2012Date of Patent: September 17, 2013Assignee: Cypress Semiconductor CorporationInventors: Edward L. Grivna, David G. Wright, Ronald H. Sartore
-
Publication number: 20130229880Abstract: A memory module includes volatile memory and non-volatile memory. The module includes logic to check if a non-volatile memory comprises un-erased areas, and if the non-volatile memory comprises un-erased areas, to elevate a backup capacitor potential above a predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory. The module includes logic to ERASE the un-erased areas and to return the capacitor to the predetermined operating potential after the ERASE is complete.Type: ApplicationFiled: January 14, 2013Publication date: September 5, 2013Applicant: AgigA Tech Inc.Inventor: Ronald H. Sartore
-
Patent number: 8479061Abstract: A memory cartridge is described that includes a non-volatile memory. The cartridge also includes logic to concentrate memory operations on particular areas of the non-volatile memory to cause the areas of concentration to wear out at an accelerated rate relative to non areas of concentration, and logic to track wear on the non-volatile memory resulting from one or both of erases and writes.Type: GrantFiled: September 24, 2009Date of Patent: July 2, 2013Assignee: AgigA TechInventor: Ronald H Sartore
-
Publication number: 20130111109Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.Type: ApplicationFiled: May 27, 2012Publication date: May 2, 2013Applicant: AGIGA TECH INC.Inventor: Ronald H. Sartore
-
Publication number: 20130111111Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.Type: ApplicationFiled: May 28, 2012Publication date: May 2, 2013Applicant: AgigA Tech Inc.Inventor: Ronald H. Sartore
-
Publication number: 20130111110Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.Type: ApplicationFiled: May 28, 2012Publication date: May 2, 2013Applicant: AgigA Tech Inc.Inventor: Ronald H. Sartore
-
Patent number: 8200929Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.Type: GrantFiled: November 2, 2011Date of Patent: June 12, 2012Assignee: Agiga Tech IncInventor: Ronald H Sartore