Abstract: A memory subsystem includes a volatile memory and a nonvolatile memory. A controller includes logic to interface the volatile memory to an external system, so that the volatile memory is addressable for reading and writing by the external system. The controller includes logic to back up data from the volatile memory to the nonvolatile memory upon receiving a backup signal from the external system. A power controller includes logic to detect when power from the external system fails, and when power from the external system fails, to provide backup power for long enough to enable the controller to back up data from the volatile memory to a first region of the nonvolatile memory. The controller, upon receiving the backup signal from the external system, backs up data from the volatile memory to a second region of the nonvolatile memory different that the first region used to back up data from the volatile memory to the nonvolatile memory when power from the external system fails.

Abstract: An apparatus and method for distinguishing a particular gesture from among multiple gestures, performed by a conductive object on the sensing device, using fewer than three time intervals. The apparatus may include a sensing device to detect a presence of a conductive object, and a processing device, coupled to the sensing device, to distinguish the multiple gestures. The method may include distinguishing between a tap gesture, a double tap gesture, a drag gesture, and a motion gesture.

Abstract: A memory subsystem is configured to obtain power from an external system and from at least one power capacitors. The memory subsystem includes logic to verify the power delivery capability of the power capacitors.

Abstract: An apparatus and method for providing an active feedback of a position of a conductive object, manipulated by a user on a sensing device, to allow detection of a reference location on the sensing device by the user. The apparatus may include a sensing device to detect a presence of a conductive object, manipulated by a user on the sensing device, a processing device coupled to the sensing device, the processing device to determine a position of the conductive object on the sensing device, and a feedback mechanism coupled to the processing device to provide an active feedback to the user to allow detection of a reference location on the sensing device by the user.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Abstract: A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.

Abstract: An apparatus includes a capacitor and logic to adjust an operating temperature of the capacitor according to a charge on the capacitor, and/or to adjust a charge of the capacitor according to the operating temperature of the capacitor to improve the useful life of the capacitor and increase its reliability.

Abstract: A memory system includes logic to distribute bits of a data word from a first memory across multiple pages of a flash memory.

Abstract: A memory cartridge is described that includes a non-volatile memory. The cartridge also includes logic to concentrate memory operations on particular areas of the non-volatile memory to cause the areas of concentration to wear out at an accelerated rate relative to non areas of concentration, and logic to track wear on the non-volatile memory resulting from one or both of erases and writes.

Abstract: A memory system includes a volatile memory and a non-volatile memory. The volatile memory is configured as a random access memory or cache for the nonvolatile memory. Wear concentration logic targets one or more selected devices of the nonvolatile memory for accelerated wear.

Abstract: In one embodiment, a method for controlling display of data includes identifying a data item selected by a user from multiple data items displayed on a display screen, and modifying the appearance of the multiple data items. The method further includes causing the multiple data items to be displayed on the display screen in the modified form, together with additional information pertaining to the selected data item, where the additional information is presented without obscuring the multiple data items displayed on the display screen.

Abstract: A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.

Abstract: A method, apparatus or system for generating a clock signal that includes determining a transmission frequency within a first frequency range for receiving or transmitting a data stream, locking a clock to the transmission frequency during a packet exchange and tuning the clock to one or more frequencies within a second frequency range after the packet exchange. The clock may be variably tuned to multiple frequencies within either the first or second range.

Abstract: An apparatus includes a capacitor and logic to adjust an operating temperature of the capacitor according to a charge on the capacitor, and/or to adjust a charge of the capacitor according to the operating temperature of the capacitor to improve the useful life of the capacitor and increase its reliability.

Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.

Abstract: A memory subsystem includes a volatile memory and a nonvolatile memory. A controller includes logic to interface the volatile memory to an external system, so that the volatile memory is addressable for reading and writing by the external system. The controller includes logic to back up data from the volatile memory to the nonvolatile memory upon receiving a backup signal from the external system. A power controller includes logic to detect when power from the external system fails, and when power from the external system fails, to provide backup power for long enough to enable the controller to back up data from the volatile memory to a first region of the nonvolatile memory. The controller, upon receiving the backup signal from the external system, backs up data from the volatile memory to a second region of the nonvolatile memory different that the first region used to back up data from the volatile memory to the nonvolatile memory when power from the external system fails.

Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Abstract: A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.

Abstract: A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.