Patents by Inventor Roy Greeff
Roy Greeff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7969284Abstract: A wireless communication system includes an interrogator including a housing including circuitry configured to generate a forward link communication signal; communication circuitry configured to communicate the forward link communication signal; and a communication station remotely located with respect to the housing and configured to receive the forward link communication signal from the communication circuitry and to radiate a forward link wireless signal corresponding to the forward link communication signal; and at least one remote communication device configured to receive the forward link wireless signal.Type: GrantFiled: August 30, 2007Date of Patent: June 28, 2011Assignee: Round Rock Research, LLCInventors: David K. Ovard, Roy Greeff
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Publication number: 20110140858Abstract: The present invention provides backscatter interrogators, communication systems and backscatter communication methods. According to one aspect of the present invention, a backscatter interrogator includes a data path configured to communicate a data signal; a signal generator configured to generate a carrier signal; and a modulator coupled with the data path and the signal generator, the modulator being configured to spread the data signal to define a spread data signal and amplitude modulate the carrier signal using the spread data signal, the modulator being further configured to phase modulate the carrier signal.Type: ApplicationFiled: February 22, 2011Publication date: June 16, 2011Inventors: David K. Ovard, Roy Greeff
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Publication number: 20110145453Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.Type: ApplicationFiled: February 2, 2011Publication date: June 16, 2011Applicant: ROUND ROCK RESEARCH, LLCInventors: Roy Greeff, Terry R. Lee
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Patent number: 7913005Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.Type: GrantFiled: November 3, 2008Date of Patent: March 22, 2011Assignee: Round Rock Research, LLCInventors: Roy Greeff, Terry R. Lee
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Patent number: 7898390Abstract: An interrogator provides a phase shifter including a first power divider configured to receive a signal and provide plural quadrature components of the signal; plural mixers coupled with the first power divider and configured to scale the quadrature components using a phase shift angle; and a second power divider coupled with the mixers and configured to combine the scaled quadrature components to shift the phase angle of the input signal by the phase shift angle.Type: GrantFiled: August 10, 2006Date of Patent: March 1, 2011Assignee: Round Rock Research, LLCInventors: Roy Greeff, David K. Ovard
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Publication number: 20100223406Abstract: Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory units. In some examples, a quarter-wavelength stub is used to implement the filter. In some examples, signal components at 800 MHz may be attenuated by a stub, which may improve ringback.Type: ApplicationFiled: February 27, 2009Publication date: September 2, 2010Applicant: Micron Technology, Inc.Inventor: Roy Greeff
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Publication number: 20090276545Abstract: A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.Type: ApplicationFiled: May 5, 2008Publication date: November 5, 2009Inventors: Terry R. Lee, David Ovard, Roy Greeff, Robert N. Leibowitz, Victor Tsai
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Patent number: 7592898Abstract: A wireless communication system includes an interrogator including a housing including circuitry configured to generate a forward link communication signal; communication circuitry configured to communicate the forward link communication signal; and a communication station remotely located with respect to the housing and configured to receive the forward link communication signal from the communication circuitry and to radiate a forward link wireless signal corresponding to the forward link communication signal; and at least one remote communication device configured to receive the forward link wireless signal.Type: GrantFiled: March 9, 1999Date of Patent: September 22, 2009Assignee: Keystone Technology Solutions, LLCInventors: David K. Ovard, Roy Greeff
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Publication number: 20090184745Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.Type: ApplicationFiled: April 1, 2009Publication date: July 23, 2009Applicant: Micron Technology, Inc.Inventors: Roy Greeff, David Ovard
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Patent number: 7514979Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.Type: GrantFiled: April 30, 2008Date of Patent: April 7, 2009Assignee: Micron Technology, Inc.Inventors: Roy Greeff, David Ovard
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Publication number: 20090070503Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.Type: ApplicationFiled: November 3, 2008Publication date: March 12, 2009Inventors: Roy Greeff, Terry R. Lee
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Publication number: 20090025204Abstract: A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one another on a surface of the printed circuit board. A dielectric coating is applied to at least one of the at least two microstrip lines such that the dielectric constant of the dielectric coating differs from the dielectric constant of free space. In a further embodiment, the dielectric coating comprises a material having a dielectric constant approximately equal to the dielectric constant of the printed circuit board.Type: ApplicationFiled: September 30, 2008Publication date: January 29, 2009Inventor: Roy Greeff
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Patent number: 7461188Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.Type: GrantFiled: August 20, 2007Date of Patent: December 2, 2008Assignee: Micron Technology, Inc.Inventors: Roy Greeff, Terry R. Lee
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Patent number: 7436267Abstract: A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one another on a surface of the printed circuit board. A dielectric coating is applied to at least one of the at least two microstrip lines such that the dielectric constant of the dielectric coating differs from the dielectric constant of free space. In a further embodiment, the dielectric coating comprises a material having a dielectric constant approximately equal to the dielectric constant of the printed circuit board.Type: GrantFiled: July 20, 2006Date of Patent: October 14, 2008Assignee: Micron Technology, Inc.Inventor: Roy Greeff
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Patent number: 7432774Abstract: A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one another on a surface of the printed circuit board. A dielectric coating is applied to at least one of the at least two microstrip lines such that the dielectric constant of the dielectric coating differs from the dielectric constant of free space. In a further embodiment, the dielectric coating comprises a material having a dielectric constant approximately equal to the dielectric constant of the printed circuit board.Type: GrantFiled: February 27, 2004Date of Patent: October 7, 2008Assignee: Micron Technology, Inc.Inventor: Roy Greeff
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Patent number: 7424634Abstract: A method and system for coupling digital signals from a first location to a second location through respective signal lines includes a mode detector that detects each of the transitions of the digital signals. The mode detector determines respective propagation times of the signals through the signal lines based on the relative transitions of the signals. The mode detector then applies delay values to delay circuits that couple the signals to the signal lines with respective delays corresponding to the delay values. The delay values may be determined by coupling a predetermined pattern of test signals through the signal lines and determining which delay values allow the signals to be most accurately captured at the second location.Type: GrantFiled: March 14, 2005Date of Patent: September 9, 2008Assignee: Micron Technology, Inc.Inventors: Roy Greeff, David Ovard
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Publication number: 20080204108Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.Type: ApplicationFiled: April 30, 2008Publication date: August 28, 2008Applicant: Micron Technology, Inc.Inventors: Roy Greeff, David Ovard
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Publication number: 20080180253Abstract: A radio frequency identification (RFID) system enabling backscatter communication between a reader and a tag. A baseband data signal is encoded, and it may be selectively inverted and used to modulate a carrier using amplitude modulation, phase modulation, or both amplitude and phase modulation. A reply received from the tag in response to a command from the reader may include an identification code associated with an object to which the tag is affixed.Type: ApplicationFiled: July 23, 2007Publication date: July 31, 2008Applicant: MICRON TECHNOLOGY, INC.Inventors: David K. Ovard, Roy Greeff
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Patent number: 7375573Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.Type: GrantFiled: May 25, 2006Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventors: Roy Greeff, David Ovard
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Publication number: 20080036492Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: ApplicationFiled: October 9, 2007Publication date: February 14, 2008Applicant: Micron Technology, Inc.Inventors: George Pax, Roy Greeff