Abstract: The embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic wide band frequency modulation. The chaotic noise modulator, in one embodiment, comprises: a master cell to generate a control voltage corresponding to an un-modulated reference signal; and a slave cell having a chaotic signal generator to generate a random noise signal, the slave cell coupled with the master cell and operable to generate a modulated output signal in response to the control voltage.

Abstract: Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.

Abstract: Embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic frequency modulation. In one embodiment, an apparatus comprises a first cell comprising a chaotic signal generator to generate a chaotic signal and a phase-locked loop (PLL) to generate a modulated output signal based at least on an un-modulated reference signal and the chaotic signal.

Abstract: The embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic wide band frequency modulation. The chaotic noise modulator, in one embodiment, comprises: a master cell to generate a control voltage corresponding to an un-modulated reference signal; and a slave cell having a chaotic signal generator to generate a random noise signal, the slave cell coupled with the master cell and operable to generate a modulated output signal in response to the control voltage.

Abstract: An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.

Abstract: A digital circuit operating frequency characterizer provides a combination of frequency and duty cycle characterization. The digital circuit operating frequency characterizer includes a programmable frequency generator, a programmable edge variator, a test engine, and a control circuit. The programmable frequency generator provides one or more output signals, and the programmable edge variator is coupled to one or more outputs of the programmable frequency generator for adjusting duty cycle. The test engine uses the outputs from the programmable edge variator and/or programmable frequency generator to apply a defined test signal sequence to a circuit under test and produce a status output after evaluating the outputs received from the circuit under test. The control circuit is connected to the control inputs of the programmable frequency generator, programmable edge variator, and the status output of the test engine.

Abstract: A digital circuit operating frequency characterizer provides a combination of frequency and duty cycle characterization. The digital circuit operating frequency characterizer includes a programmable frequency generator, a programmable edge variator, a test engine, and a control circuit. The programmable frequency generator provides one or more output signals, and the programmable edge variator is coupled to one or more outputs of the programmable frequency generator for adjusting duty cycle. The test engine uses the outputs from the programmable edge variator and/or programmable frequency generator to apply a defined test signal sequence to a circuit under test and produce a status output after evaluating the outputs received from the circuit under test. The control circuit is connected to the control inputs of the programmable frequency generator, programmable edge variator, and the status output of the test engine.

Abstract: An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.