Abstract: A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.

Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.

Abstract: Examples may construct a logical system by interconnecting endpoint resources in a memory semantic environment. Examples include identifying a first path for interconnecting endpoint resources based on at least a cost for interconnecting the endpoint resources.

Abstract: A system includes byte-addressable non-volatile memory (NVM) modules. The system includes media controllers communicatively connected to one another over a memory semantic fabric. Each media controller is responsible for a corresponding NVM module to which the media controller is attached. The media controllers cooperatively provide redundant array of independent disks (RAID) functionality at a granularity at which the NVM modules are byte-addressable without employing a master RAID controller.

Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.

Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.

Abstract: A system includes byte-addressable non-volatile memory (NVM) modules. The system includes media controllers communicatively connected to one another over a memory semantic fabric. Each media controller is responsible for a corresponding NVM module to which the media controller is attached. The media controllers cooperatively provide redundant array of independent disks (RAID) functionality at a granularity at which the NVM modules are byte-addressable without employing a master RAID controller.

Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.

Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.

Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.

Abstract: A non-volatile memory (NVM) is to store data and a first password. The first password is to protect the data. A controller is to selectively enable interaction with the data based on authenticating the first password against a second password. A temporary region is to store the second password. The second password is discarded in response to a status change of the apparatus. The data, the first password, and the second password are resettable by the controller in response to a reset request to bypass the first password, such that the apparatus is restorable to an unused state without authenticating the first password.

Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.

Abstract: A security framework for a multi-tenant, multi-tier computer system with embedded processing is described. A multi-tenant security framework is created for a combined processing and storage hierarchy of multiple tiers. The multi-tenant security framework is applied to multiple execution levels of the memory device. The multi-tenant security framework is applied to multiple layers of application server software of the memory device. The multi-tenant security framework is also applied to multiple layers of storage server software of the memory device.

Abstract: Examples disclosed herein relate to an error coordination message for a blade device having a logical processor in another system firmware (SFW) domain. Examples include a partition of a blade system to run an operating system (OS) utilizing blade devices including respective logical processors operating in different SFW domains. Examples further include an error coordination message made available to one of the blade devices by another of the blade devices.

Abstract: A method for rendering data invalid within a memory array is described. The method includes establishing governing metadata for a memory location within a memory array. The method also includes receiving a request to retrieve data from the memory location. The method also includes determining whether color metadata associated with the data matches the governing metadata. The method also includes returning the data when the color metadata matches the governing metadata. The method also includes returning invalidated data when the color metadata does not match the governing metadata.

Abstract: Example implementations relate to a method of tracking data in a non-volatile memory device (NVM) device. A meta-data block from the NVM device is obtained, where the meta-data block includes meta-data. The meta-data block from the NVM device is used to track an associated data object, meta-data in the data block, a user data block, a meta-data block, or an additional data block. The meta-data block from the NVM device is used to point to the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block. The meta-data block from the NVM device is further used to link the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block.

Abstract: A method for rendering data invalid within a memory array is described. The method includes establishing governing metadata for a memory location within a memory array. The method also includes receiving a request to retrieve data from the memory location. The method also includes determining whether color metadata associated with the data matches the governing metadata. The method also includes returning the data when the color metadata matches the governing metadata. The method also includes returning invalidated data when the color metadata does not match the governing metadata.

Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.

Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.

Abstract: Examples disclosed herein provide moving a block of data between a source address and a target address. The examples disclose initiating a data move engine to move the block of data from the source address to the target address. Additionally, the examples disclose moving the block of data from the source address to the target address in a manner which allows a processor to concurrently access the block of data during the move.