Abstract: A unifying memory controller (UMC) to send and receive data to and from a local host. The UMC also may manage data placement and retrieval by using an address mapper. The UMC may also selectively provide power to a plurality of memory locations. The UMC may also manage data placement based on a policy that can make use of a property stored in the metadata storage location. The property may be a property describing the data that is being managed. The UMC also may use its own local cache that may store copies of data managed by the circuit.

Abstract: According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.

Abstract: A security framework for a multi-tenant, multi-tier computer system with embedded processing is described. A multi-tenant security framework is created for a combined processing and storage hierarchy of multiple tiers. The multi-tenant security framework is applied to multiple execution levels of the memory device. The multi-tenant security framework is applied to multiple layers of application server software of the memory device. The multi-tenant security framework is also applied to multiple layers of storage server software of the memory device.

Abstract: Example implementations relate to a method of tracking data in a non-volatile memory device (NVM) device. A meta-data block from the NVM device is obtained, where the meta-data block includes meta-data. The meta-data block from the NVM device is used to track an associated data object, meta-data in the data block, a user data block, a meta-data block, or an additional data block. The meta-data block from the NVM device is used to point to the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block. The meta-data block from the NVM device is further used to link the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block.

Abstract: Examples disclosed herein relate to making memory of compute and expansion blade devices available for use by an operating system (OS). Examples include making available, for use by an OS, a compute logical processor of the compute blade device, identified memory of the compute blade device, and identified memory of an expansion blade device. Examples further include making the expansion logical processor unavailable to the OS.

Abstract: Examples disclosed herein relate to identifying memory of a blade device for use by an operating system (OS) of a partition including the blade device. Examples include identifying memory of a first blade device associated with a first logical processor of the first blade device for use by an OS of a partition including the first blade device and a second blade device, wherein the OS is executed by at least a second logical processor of the second blade device.

Abstract: A unifying memory controller (UMC) to send and receive data to and from a local host. The UMC also may manage data placement and retrieval by using an address mapper. The UMC may also selectively provide power to a plurality of memory locations. The UMC may also manage data placement based on a policy that can make use of a property stored in the metadata storage location. The property may be a property describing the data that is being managed. The UMC also may use its own local cache that may store copies of data managed by the circuit.

Abstract: Examples disclosed herein relate to an error coordination message for a blade device having a logical processor in another system firmware (SFW) domain. Examples include a partition of a blade system to run an operating system (OS) utilizing blade devices including respective logical processors operating in different SFW domains. Examples further include an error coordination message made available to one of the blade devices by another of the blade devices.

Abstract: A blade computer system comprises side-by-side computer blades (44, 144), a connectivity module (50, 150, 350) extending across and connected to each of the plurality of side-by-side computer blades (44, 144) along the ends of the computer blades (44, 144) and at least one first power supply-fan unit (46, 146) extending perpendicular to the first axis and directly connected to each of the first plurality of side-by-side computer blades (44, 144) along ends of the plurality of side-by-side computer blades (44, 144) such that the at least one power supply-fan unit (46, 146) draws air across the first plurality of side-by-side computer blades (44, 144) and into the first connectivity module (50, 150, 350).

Abstract: Examples disclosed herein provide moving a block of data between a source address and a target address. The examples disclose initiating a data move engine to move the block of data from the source address to the target address. Additionally, the examples disclose moving the block of data from the source address to the target address in a manner which allows a processor to concurrently access the block of data during the move.

Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.

Abstract: According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.

Abstract: A non-volatile memory (NVM) is to store data and a first password. The first password is to protect the data. A controller is to selectively enable interaction with the data based on authenticating the first password against a second password. A temporary region is to store the second password. The second password is discarded in response to a status change of the apparatus. The data, the first password, and the second password are resettable by the controller in response to a reset request to bypass the first password, such that the apparatus is restorable to an unused state without authenticating the first password.

Abstract: A blade computer system comprises side-by-side computer blades (44, 144), a connectivity module (50, 150, 350) extending across and connected to each of the plurality of side-by-side computer blades (44, 144) along the ends of the computer blades (44, 144) and at least one first power supply-fan unit (46, 146) extending perpendicular to the first axis and directly connected to each of the first plurality of side-by-side computer blades (44, 144) along ends of the plurality of side-by-side computer blades (44, 144) such that the at least one power supply-fan unit (46, 146) draws air across the first plurality of side-by-side computer blades (44, 144) and into the first connectivity module (50, 150, 350).

Abstract: Examples disclosed herein relate to identifying memory of a blade device for use by an operating system (OS) of a partition including the blade device. Examples include identifying memory of a first blade device associated with a first logical processor of the first blade device for use by an OS of a partition including the first blade device and a second blade device, wherein the OS is executed by at least a second logical processor of the second blade device.

Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.

Abstract: Examples disclosed herein relate to making memory of compute and expansion blade devices available for use by an operating system (OS). Examples include making available, for use by an OS, a compute logical processor of the compute blade device, identified memory of the compute blade device, and identified memory of an expansion blade device. Examples further include making the expansion logical processor unavailable to the OS.

Abstract: A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.

Abstract: A method for sending data from a local memory device in a first computing device to an external memory device in a second computing device is described herein. In one example, a method includes configuring the local memory device to store data for the external memory device and detecting a request for data from the external memory device. The method also includes translating a memory address that corresponds to the requested data from an external memory address to a local memory address. Additionally, the method includes retrieving the requested data based on the local memory address and sending the requested data to the second computing device.

Abstract: The present disclosure provides techniques for mapping large shared address spaces in a computing system. A method includes creating a physical address map for each node in a computing system. Each physical address map maps the memory of a node. Each physical address map is copied to a single address map to form a global address map that maps all memory of the computing system. The global address map is shared with all nodes in the computing system.