Abstract: A power throttling method and system for a memory controller in a computer system. One embodiment includes, responsive to a determination that a change in the state of a cover switch has occurred that will result in an increase in an operating temperature of at least one memory device during normal operation, driving a throttle control signal to the memory controller to a level indicative of an over-threshold state.

Abstract: In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.

Abstract: A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, so that every device that can request a copy of memory data maintains a local copy of the GOTL. The GOTL can be limited to a relatively small size. For a limited size list, a tag may need to be evicted to make room for a new tag. A line associated with an evicted tag must be written back to memory.

Abstract: A system for sharing data between partitions is provided. The system comprises a plurality of partitions and a storage accessible to the plurality of partitions. Each partition comprises an inter-partition data sharing logic comprising one or more registers that receive data packets for sharing between partitions, and a connection to a system fabric operably coupling the inter- partition data sharing logic to the storage. The system fabric couples the partitions, through the storage, to one another instead of use of a network connection. Alternatively, a management subsystem may also be used to couple the partitions to one another instead of use of a network connection.

Abstract: A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, so that every device that can request a copy of memory data maintains a local copy of the GOTL. The GOTL can be limited to a relatively small size. For a limited size list, a tag may need to be evicted to make room for a new tag. A line associated with an evicted tag must be written back to memory.

Abstract: A lower level cache detects when a line of memory has been evicted from a higher level cache. The lower level cache stores the address of the evicted line. When the system bus is idle, the lower level cache initiates a transaction causing all higher level caches to invalidate the line. The lower level cache then places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed.

Abstract: A system and method for virtual device access in a graphics computer is disclosed. The present invention enables applications running on a graphics computer to access the graphics hardware device with no per-transaction performance cost. Each time an application attempts to access the graphics hardware device, a hardware control manager either gives the application access to the graphics hardware device if no other application is currently accessing the hardware, or alternatively, if another application is currently accessing hardware, the hardware control manager instructs a signal handler associated with the application attempting access to perform a graphics context switch with the currently accessing application before the hardware control manager will give permission to the application attempting access to access the graphics hardware device.

Abstract: The present invention relates to an intelligent direct memory access (DMA) controller which interprets user commands from a host system, establishes work buffers for each user process, and retrieves blocks of data from the work buffers at the user's is request, rather than at the request of the kernel software. This is accomplished by establishing work buffers for each user process which are locked into physical memory. The controlling user process will then fill one work buffer, acquire the device semaphore, start physical DMA on the locked buffer, and then start filling another buffer. Memory integrity is maintained by allowing the user to access the work buffers for DMA without knowing their physical location in memory, via work buffer pointers from work buffer pointer registers which correspond to each work buffer for each user process. These work buffer pointer registers are privileged and are updated by the host processor for each new controlling user process.

Abstract: A device for distributing a serial stream of commands and associated data to a parallel array of processing units so that the data processed by the parallel processing units can be recombined in the original order in which the serial stream was received. The command distributor of the invention hands out commands to the parallel processing units using a true "first come, first serve" algorithm using fast bus arbitration hardware. Each parallel processing unit requests data to be input when all of its data has been processed, and bus arbitration is used to prevent conflict when a plurality of requests are received. The ID of the processor to which a command is assigned is used in recombining the processed data into a serial data stream having the same order as the original.

Abstract: The present invention relates to an intelligent direct memory access (DMA) controller which interprets user commands from a host system, translates virtual addresses from the user applications program to physical addresses, and retrieves blocks of data from the main system memory at the request of the user's code, rather than at the request of the kernel code of the host system. This is accomplished by representing the data processing commands of the user and the data associated therewith as respective command/pointer packets comprised of data processing commands and virtual pointers to the associated data in virtual memory space of the user's host system. The virtual pointers of the command/pointer packets may then be translated to physical pointers for purposes of identifying physical addresses within the main memory at which the associated data is located. The associated data may then be read from the physical address in the main memory without interrupting the host processor.