Abstract: A semiconductor device according to an embodiment includes: a SiC layer having a first plane, a second plane, a first trench located on a first plane side, an n-type first SiC region, a p-type second SiC region between the first SiC region and the first plane, an n-type third SiC region between the second SiC region and the first plane, and a p-type fourth SiC region between the first SiC region and the first plane, at least a portion of the fourth SiC region located in the second SiC region, the fourth SiC region having a higher p-type impurity concentration than the second SiC region; a gate electrode in the first trench; a first electrode located on the first plane side; and a second electrode located on a second plane side. A depth of the fourth SiC region increases with distance from the first trench.

Abstract: A semiconductor device according to an embodiment includes: a SiC layer having a first plane and a second plane facing the first plane, the SiC layer including a first trench on a first plane side, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region located in this order from the second plane to the first plane, a p-type fourth SiC region between the first SiC region and the first trench, a fifth SiC region between the first SiC region and the first plane, and a sixth SiC region between the fourth SiC region and the fifth SiC region, and the sixth SiC region having an n-type impurity concentration higher than an n-type impurity concentration of the first SiC region; a gate electrode in the first trench; a first electrode on the first plane side; and a second electrode on a second plane side.

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane, a second plane facing the first plane, a first trench, a second trench, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, an n-type third silicon carbide region between the second silicon carbide region and the first plane, and a p-type fourth silicon carbide region between the second trench and the first silicon carbide region; a gate electrode being located in the first trench; a gate insulating layer; a first electrode, a portion of the first electrode being located in the second trench; a second electrode; and an interlayer insulating layer being located between the gate electrode and the first electrode, in which an interface between the first electrode and the interlayer insulating layer is located in the first trench.

Abstract: A semiconductor device according to an embodiment includes a gate electrode, a gate insulating layer, and a silicon carbide layer. The silicon carbide layer includes at least one first element selected from the group consisting of S, Se, Te, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, and W. The first distance between a first position and an interface between the gate insulating layer and the silicon carbide layer is equal to or less than 20 nm, and the first position is a position where a concentration of the first element is maximized. The second distance between a second position and the interface is equal to or less than 20 nm, second position is a position where a concentration of the first element is 1/10 of a concentration of the first element at the first position, and the second position is farther from the interface than the first position.

Abstract: A semiconductor device includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes first and second layers and first and second regions. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is across the first layer and the second layer, and includes at least one first element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth) and the first region having a first concentration peak of the at least one first element. The second region is provided in the first layer, includes a second element from Ta (tantalum), Nb (niobium), and V (vanadium) and, the second region having a second concentration peak of the at least one second element.

Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having first and second plane, the silicon carbide layer including trench having a first portion and a second portion, the second portion having a width smaller than the first portion, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, a p-type third silicon carbide region between the second silicon carbide region and the first plane and having a p-type impurity concentration lower than the second silicon carbide region, an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and an n-type fifth silicon carbide region between the second portion and the second silicon carbide region and having an n-type impurity concentration higher than the first silicon carbide region; and a gate electrode in the trench.

Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane and includes a trench located on a first plane side and has a first region and a second region, a first silicon carbide region of an n-type, a second silicon carbide region of a p-type between the first silicon carbide region and the first plane, a third silicon carbide region of the n-type between the second silicon carbide region and the first plane, and a fourth silicon carbide region of the p-type between the second region and the first silicon carbide region; a gate electrode in the first region; a first electrode on the first plane side of the silicon carbide layer, a part of the first electrode is located in the second region and is in contact with the third and the fourth silicon carbide region; and a second electrode.

Abstract: A semiconductor device of an embodiment includes a SiC layer including a first trench, a second trench having first and second regions, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region, a p-type fourth SiC region between the first trench and the first SiC region, and a p-type fifth SiC region between the second trench and the first SiC region and having a first portion and a second portion, a gate electrode in the first trench, a first electrode in the second trench, and a second electrode. A distance between the first trench and the first region is greater than a distance between the first trench and the second region, the first portion is separated from the fourth SiC region, the second portion contacts the fourth SiC region, the first region contacts the first portion, and the second region contacts the second portion.

Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and the silicon carbide layer having a first plane and a second plane, the silicon carbide layer including a first trench, p-type first silicon carbide regions and n-type second silicon carbide regions alternately disposed, a p-type third silicon carbide region between the second silicon carbide region and the first plane, and an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and a p-type fifth silicon carbide region between the first silicon carbide region and the first trench, a gate electrode in the first trench, and a gate insulating layer. The length of the first silicon carbide region perpendicular to the first plane is longer than a depth of the first trench.

Abstract: According to one embodiment, a semiconductor device includes a first layer, a first electrode, and a first nitride region. The first layer includes a first material and a first partial region. The first material includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first partial region is of a first conductivity type. The first conductivity type is one of an n-type or a p-type. A direction from the first partial region toward the first electrode is aligned with a first direction. The first nitride region includes Alx1Ga1-x1N (0?x1<1), is provided between the first partial region and the first electrode, is of the first conductivity type, and includes a first protrusion protruding in the first direction.

Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first and second plane, first and second trench extending in first direction, and in the silicon carbide layer, n-type first region, p-type second region between the n-type first region and the first plane and between the first and second trench, p-type fifth region covering bottom of the first trench, p-type sixth region covering bottom of the second trench, n-type seventh region between the fifth region and the second region, n-type eighth region between the sixth and second regions, p-type ninth regions contacting the fifth and second regions, and p-type tenth regions contacting the sixth region and the second region, the ninth and tenth regions repeatedly disposed in the first direction, and a line segment connecting the ninth region and the tenth region is oblique with respect to second direction perpendicular to the first direction.

Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first and a second plane, a trench, a gate electrode in the trench, an n-type first silicon carbide region, a p-type second silicon carbide region and a p-type third silicon carbide region provided between the first silicon carbide region and the first plane and interposing the trench therebetween, a p-type sixth silicon carbide region between the first silicon carbide region and the second silicon carbide region, a p-type seventh silicon carbide region between the first silicon carbide region and the third silicon carbide region, an eighth silicon carbide region between the first silicon carbide region and the sixth silicon carbide region, and a ninth silicon carbide region between the first silicon carbide region and the seventh silicon carbide region. The eighth silicon carbide region has a plurality of first regions extending toward the ninth silicon carbide region.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include performing a first heat treatment of a first film at a first temperature not less than 500° C. and not more than 900° C. in a first atmosphere including oxygen. The first film includes silicon and oxygen and is deposited on a semiconductor member including silicon carbide. The method can include performing, after the first heat treatment, a second heat treatment of the first film at a second temperature not less than 1200° C. but less than 1400° C. in a second atmosphere including nitrogen.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include a first process of causing a stacking fault of a first semiconductor layer to expand. The first semiconductor layer includes silicon carbide and a first element and is provided on a base body including silicon carbide. The first element includes at least one selected from the group consisting of N, P, and As. The method can include a second process of forming a second semiconductor layer on the first semiconductor layer after the first process. The second semiconductor layer includes silicon carbide and the first element. The method can include a third process of forming a third semiconductor layer on the second semiconductor layer. The third semiconductor layer includes silicon carbide and a second element. The second element includes at least one selected from the group consisting of B, Al, and Ga.

Abstract: According to one embodiment, a semiconductor device includes a first layer, a first electrode, and a first nitride region. The first layer includes a first material and a first partial region. The first material includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first partial region is of a first conductivity type. The first conductivity type is one of an n-type or a p-type. A direction from the first partial region toward the first electrode is aligned with a first direction. The first nitride region includes Alx1/Ga1-x1/N (0?x1<1), is provided between the first partial region and the first electrode, is of the first conductivity type, and includes a first protrusion protruding in the first direction.

Abstract: A semiconductor device of an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen (N); and a second region disposed between the first region and the gate insulating layer, and containing at least one element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), hydrogen (H), deuterium (D), and fluorine (F).

Abstract: An embodiment is a semiconductor device includes a silicon carbide layer having a first plane and a second plane facing the first plane; a gate electrode; an aluminum nitride layer located between the silicon carbide layer and the gate electrode, the aluminum nitride layer containing an aluminum nitride crystal; a first insulating layer located between the silicon carbide layer and the aluminum nitride layer; and a second insulating layer located between the aluminum nitride layer and the gate electrode and having a wider band gap than the aluminum nitride layer.

Abstract: An embodiment of a semiconductor device including a silicon carbide layer having a first and a second planes; a first silicon carbide region of first conductivity type in the silicon carbide layer; a second silicon carbide region of second conductivity type in the silicon carbide layer between the first silicon carbide region and the first plane; a third silicon carbide region of the first conductivity type in the silicon carbide layer located between the second silicon carbide region and the first plane; a first electrode located on a side of the first plane; a second electrode located on a side of the second plane; a gate electrode; an aluminum nitride layer containing an aluminum nitride crystal between the second silicon carbide region and the gate electrode; and an insulating layer between the aluminum nitride layer and the gate electrode and having a wider band gap than the aluminum nitride layer.

Abstract: A semiconductor device according to an embodiment includes a SiC layer, an electrode electrically connected to the SiC layer and an impurity region provided between the SiC layer and the electrode. The impurity region includes first position and second position, the first position having highest concentration of an impurity in the impurity region, the highest concentration being not lower than 1×1020 cm?3 and not higher than 5×1022 cm?3, the second position having concentration of the impurity one digit lower than the highest concentration, the first position being between the electrode and the second position, a distance between the first position and the second position being 50 nm or shorter.