Patents by Inventor Ryosuke Iijima
Ryosuke Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10312330Abstract: In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method.Type: GrantFiled: February 27, 2018Date of Patent: June 4, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Johji Nishio, Ryosuke Iijima, Kazuto Takao, Takashi Shinohe
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Patent number: 10304950Abstract: According to one embodiment, a semiconductor device includes a first electrode, a semiconductor layer, and a first insulating portion. The first electrode includes first and second electrode regions. The semiconductor layer includes first to third semiconductor regions, and third and fourth partial regions. The first semiconductor region includes first and second partial regions. The first partial region is separated from the first electrode region. The second semiconductor region is separated from the second partial region. The third semiconductor region is provided between the second partial region and the second semiconductor region. The third partial region is separated from the second electrode region. The fourth partial region is separated from the second electrode region. The first insulating portion is provided between the electrode region and the partial region and between the electrode region and the semiconductor region. The first insulating portion has a first width and a second width.Type: GrantFiled: August 31, 2017Date of Patent: May 28, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Kyogoku, Ryosuke Iijima
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Patent number: 10249717Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.Type: GrantFiled: January 30, 2018Date of Patent: April 2, 2019Assignees: Kabushiki Kaisha Toshiba, Fuji Electric Co., Ltd.Inventors: Keiko Ariyoshi, Ryosuke Iijima, Shinya Kyogoku, Shinsuke Harada, Yusuke Kobayashi
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Patent number: 10243038Abstract: According to one embodiment, a semiconductor device includes a first conductive portion, a semiconductor portion including silicon carbide, and a first insulating portion. The semiconductor portion includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is provided between the second partial region and the second semiconductor region. The fourth semiconductor region is provided between the first conductive portion and the first partial region. The first insulating portion includes first to third portions. A portion of the first portion is positioned between the first conductive portion and the fourth semiconductor region. The second portion is positioned between the second semiconductor region and the portion of the first conductive portion and between the first conductive portion and the third semiconductor region. The third portion is provided between the first and second portions.Type: GrantFiled: February 27, 2018Date of Patent: March 26, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhisa Tanaka, Ryosuke Iijima, Shinya Kyogoku, Shinsuke Harada
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Patent number: 10243037Abstract: According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes a first partial region and a second partial region. The second semiconductor region is separated from the first partial region. The third semiconductor region is provided between the first partial region and the second semiconductor region. The third semiconductor region includes a third partial region and a fourth partial region. The first electrode is separated from the second partial region and is separated from the second semiconductor region and the third semiconductor region. The first insulating film includes a first insulating region and a second insulating region. The fourth semiconductor region includes a first portion. The first portion is provided between the fourth partial region and at least a portion of the first insulating film.Type: GrantFiled: August 30, 2017Date of Patent: March 26, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Kyogoku, Ryosuke Iijima
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Patent number: 10236339Abstract: According to one embodiment, a semiconductor device includes first to sixth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes first and second partial regions. The second semiconductor region is separated from the first partial region in a second direction crossing a first direction. The third semiconductor region is provided between the first partial region and the second semiconductor region. The fourth semiconductor region is provided between the first partial region and the third semiconductor region. The first electrode is separated from the second partial region, the second and third semiconductor regions, and a portion of the fourth semiconductor region. The first insulating film contacts the third semiconductor region. The fifth semiconductor region is provided between the first insulating film and the second partial region. The sixth semiconductor region is provided between the first insulating film and the fifth semiconductor region.Type: GrantFiled: August 31, 2017Date of Patent: March 19, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Kyogoku, Ryosuke Iijima, Keiko Ariyoshi
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Patent number: 10229994Abstract: A semiconductor device of an embodiment includes an SiC layer having a first and a second plane, an n-type first SiC region in the SiC layer, p-type second SiC regions between the first SiC region and the first plane, n-type third SiC regions between the second SiC regions and the first plane, a gate electrode provided between two p-type second SiC regions, a gate insulating film provided between the gate electrode and the second SiC regions, a metal layer provided between two p-type second SiC regions, and having a work function of 6.5 eV or more, and a first electrode electrically connected to the metal layer, and a second electrode, the SiC layer provided between the first electrode and the second electrode, and a part of the first SiC region is disposed between the gate insulating film and the metal layer.Type: GrantFiled: August 31, 2016Date of Patent: March 12, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Ryosuke Iijima
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Publication number: 20190067423Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a front surface inclined at 0° or more and 10° or less with respect to a (0001) face, a silicon oxide layer, and a region located between the front surface and the silicon oxide layer and having the number of carbon-carbon single bonds larger than the number of carbon-carbon double bonds.Type: ApplicationFiled: February 9, 2018Publication date: February 28, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Tatsuo SHIMIZU, Ryosuke IIJIMA
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Patent number: 10217811Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a front surface inclined at 0° or more and 10° or less with respect to a (0001) face, a silicon oxide layer, and a region located between the front surface and the silicon oxide layer and having the number of carbon-carbon single bonds larger than the number of carbon-carbon double bonds.Type: GrantFiled: February 9, 2018Date of Patent: February 26, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Ryosuke Iijima
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Publication number: 20190043942Abstract: According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes a first partial region and a second partial region. The second semiconductor region is separated from the first partial region. The third semiconductor region is provided between the first partial region and the second semiconductor region. The third semiconductor region includes a third partial region and a fourth partial region. The first electrode is separated from the second partial region and is separated from the second semiconductor region and the third semiconductor region. The first insulating film includes a first insulating region and a second insulating region. The fourth semiconductor region includes a first portion. The first portion is provided between the fourth partial region and at least a portion of the first insulating film.Type: ApplicationFiled: October 11, 2018Publication date: February 7, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Shinya KYOGOKU, Ryosuke IIJIMA
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Patent number: 10199466Abstract: A semiconductor device of an embodiment includes a silicon carbide layer including a first plane and a second plane; a trench including a first side face, a second side face, and a bottom face; a first silicon carbide region of a first-conductivity type; a second silicon carbide region of a second-conductivity type; a third silicon carbide region of the second-conductivity type sandwiching the trench with the second silicon carbide region; a sixth silicon carbide region of the second-conductivity type being in contact with the second side face and the bottom face; a gate electrode; and an insulating layer between the gate electrode and the second silicon carbide region, in which a portion of the first side face being in contact with the first silicon carbide region includes a first, second, and third region, and inclination angle of the second region is shallower than those of the first and third regions.Type: GrantFiled: February 27, 2018Date of Patent: February 5, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Kyogoku, Ryosuke Iijima
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Patent number: 10177251Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.Type: GrantFiled: February 8, 2018Date of Patent: January 8, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Takashi Shinohe, Ryosuke Iijima
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Publication number: 20180330949Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include performing a first heat treatment of a first film at a first temperature not less than 500° C. and not more than 900° C. in a first atmosphere including oxygen. The first film includes silicon and oxygen and is deposited on a semiconductor member including silicon carbide. The method can include performing, after the first heat treatment, a second heat treatment of the first film at a second temperature not less than 1200° C. but less than 1400° C. in a second atmosphere including nitrogen.Type: ApplicationFiled: February 12, 2018Publication date: November 15, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Shunsuke ASABA, Ryosuke IIJIMA, Yukio NAKABAYASHI, Shigeto FUKATSU, Toshihide ITO
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Patent number: 10043883Abstract: A semiconductor device according to an embodiment includes a wide bandgap semiconductor layer, a gate electrode and a gate insulating film provided between the wide bandgap semiconductor layer and the gate electrode. The gate insulating film includes a first insulating film having a thickness of 7 nm or greater, a fixed charge film provided on the first insulating film, the fixed charge film containing fixed charge and a second insulating film provided on the fixed charge film, the second insulating film having a thickness of 7 nm or greater. The gate insulating film has a total thickness of 25 nm or greater.Type: GrantFiled: July 30, 2015Date of Patent: August 7, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Teruyuki Ohashi, Ryosuke Iijima, Tatsuo Shimizu
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Publication number: 20180219070Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.Type: ApplicationFiled: January 30, 2018Publication date: August 2, 2018Applicants: Kabushiki Kaisha Toshiba, Fuji Electric Co., Ltd.Inventors: Keiko ARIYOSHI, Ryosuke IIJIMA, Sinya KYOGOKU, Shinsuke HARADA, Yusuke KOBAYASHI
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Patent number: 10026813Abstract: A semiconductor device including a p-type SiC layer, a gate electrode, and a gate insulating layer therebetween, the gate insulating layer including a first layer, a second layer provided between the first layer and the gate electrode and having a higher oxygen density than the first layer, a first and second regions provided in the second layer, the first region including a first element (at least one of Ta, Nb and V) having a first concentration peak, and the second region including a second element (at least one of Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba , La, and lanthanoid) having a second concentration peak of the second element and a third concentration peak of C, a distance between the second concentration peak and the third concentration peak being shorter than a distance between the first concentration peak and the third concentration peak.Type: GrantFiled: June 27, 2017Date of Patent: July 17, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Ryosuke Iijima
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Publication number: 20180190775Abstract: In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Johji Nishio, Ryosuke Iijima, Kazuto Takao, Takashi Shinohe
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Patent number: 10014378Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer, an insulating layer, and a region provided between the silicon carbide layer and the insulating layer, the region including a plurality of first atoms of one element from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Si), at least some of the plurality of first atoms being four-fold coordinated atoms and/or five-fold coordinated atoms.Type: GrantFiled: February 13, 2017Date of Patent: July 3, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Ryosuke Iijima
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Publication number: 20180158938Abstract: According to one embodiment, a semiconductor device includes a first electrode, a semiconductor layer, and a first insulating portion. The first electrode includes first and second electrode regions. The semiconductor layer includes first to third semiconductor regions, and third and fourth partial regions. The first semiconductor region includes first and second partial regions. The first partial region is separated from the first electrode region. The second semiconductor region is separated from the second partial region. The third semiconductor region is provided between the second partial region and the second semiconductor region. The third partial region is separated from the second electrode region. The fourth partial region is separated from the second electrode region. The first insulating portion is provided between the electrode region and the partial region and between the electrode region and the semiconductor region. The first insulating portion has a first width and a second width.Type: ApplicationFiled: August 31, 2017Publication date: June 7, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Shinya KYOGOKU, Ryosuke IIJIMA
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Patent number: 9972712Abstract: A semiconductor device according to an embodiment includes a conductive region including titanium (Ti), oxygen (O), at least one first element from zirconium (Zr) and hafnium (Hf), and at least one second element from vanadium (V), niobium (Nb), and tantalum (Ta), an n-type first SiC region, a p-type second SiC region provided between the conductive region and the n-type first SiC region, a gate electrode, and a gate insulating layer provided between the conductive region, the p-type second SiC region, the n-type first SiC region, and the gate electrode.Type: GrantFiled: August 31, 2016Date of Patent: May 15, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Ryosuke Iijima