Patents by Inventor Ryu Komatsu
Ryu Komatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120187408Abstract: An embodiment of the present invention is a microcrystalline semiconductor film having a thickness of more than or equal to 70 nm and less than or equal to 100 nm and including a crystal grain partly projecting from a surface of the microcrystalline semiconductor film. The crystal grain has an orientation plane and includes a crystallite having a size of 13 nm or more. Further, the film density of the microcrystalline semiconductor film is higher than or equal to 2.25 g/cm3 and lower than or equal to 2.35 g/cm3, preferably higher than or equal to 2.30 g/cm and lower than or equal to 2.33 g/cm3.Type: ApplicationFiled: January 20, 2012Publication date: July 26, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tetsuhiro TANAKA, Takashi Ienaga, Ryu Komatsu, Erika Kato, Ryota Tajima, Yasuhiro Jinbo
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Publication number: 20120115285Abstract: A seed crystal which includes mixed phase grains including an amorphous silicon region and a crystallite which is a microcrystal that can be regarded as a single crystal is formed on an insulating film by a plasma CVD method under a first condition that enables mixed phase grains having high crystallinity and high uniformity of grain sizes to be formed at a low density, and then a microcrystalline semiconductor film is formed to be stacked on the seed crystal by a plasma CVD method under a second condition that enables the mixed phase grains to grow to fill a space between the mixed phase grains.Type: ApplicationFiled: October 27, 2011Publication date: May 10, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Ryu KOMATSU, Yasuhiro JINBO, Hidekazu MIYAIRI
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Publication number: 20120100675Abstract: To provide a manufacturing method of a microcrystalline silicon film having both high crystallinity and high film density. In the manufacturing method of a microcrystalline silicon film according to the present invention, a first microcrystalline silicon film that includes mixed phase grains is formed over an insulating film under a first condition, and a second microcrystalline silicon film is formed thereover under a second condition. The first condition and the second condition are a condition in which a deposition gas containing silicon and a gas containing hydrogen are used as a first source gas and a second source gas. The first source gas is supplied under the first condition in such a manner that supply of a first gas and supply of a second gas are alternately performed.Type: ApplicationFiled: October 6, 2011Publication date: April 26, 2012Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Ryu KOMATSU, Yasuhiro JINBO, Hidekazu MIYAIRI, Yoshitaka YAMAMOTO
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Patent number: 8148723Abstract: A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order (a thin-film stacked body); first etching is performed to expose the first conductive film and form at least a pattern of the thin-film stacked body; second etching is performed to form a pattern of the first conductive film. The second etching is performed under a condition in which the first conductive film is side-etched. Further, after forming the patterns, an EL layer can be formed selectively by utilizing a depression and a projection due to the patterns.Type: GrantFiled: July 8, 2011Date of Patent: April 3, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shigeki Komori, Ryu Komatsu
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Publication number: 20120052637Abstract: A seed crystal including mixed phase grains having high crystallinity at a low density is formed under a first condition over an insulating film, and then a first microcrystalline semiconductor film is formed over the seed crystal under a second condition that allows the mixed phase grains to grow and a space between the mixed phase grains to be filled. Then, a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a third condition that allows formation of a microcrystalline semiconductor film having high crystallinity without increasing the space between the mixed phase grains included in the first microcrystalline semiconductor film.Type: ApplicationFiled: August 17, 2011Publication date: March 1, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Ryu KOMATSU, Yasuhiro JINBO, Hidekazu MIYAIRI
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Publication number: 20110318888Abstract: A method for manufacturing a semiconductor device comprises the steps of forming a seed over the insulating film by introducing hydrogen and a deposition gas into a first treatment chamber under a first condition and forming a microcrystalline semiconductor film over the seed by introducing hydrogen and the deposition gas into a second treatment chamber under a second condition: a second flow rate of the deposition gas is periodically changed between a first value and a second value; and a second pressure in the second treatment chamber is higher than or equal to 1.0×102 Torr and lower than or equal to 1.0×103 Torr.Type: ApplicationFiled: June 14, 2011Publication date: December 29, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Ryu KOMATSU, Yasuhiro JINBO, Hidekazu MIYAIRI
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Publication number: 20110260208Abstract: A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order (a thin-film stacked body); first etching is performed to expose the first conductive film and form at least a pattern of the thin-film stacked body; second etching is performed to form a pattern of the first conductive film. The second etching is performed under a condition in which the first conductive film is side-etched. Further, after forming the patterns, an EL layer can be formed selectively by utilizing a depression and a projection due to the patterns.Type: ApplicationFiled: July 8, 2011Publication date: October 27, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shigeki KOMORI, Ryu KOMATSU
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Patent number: 7993991Abstract: A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.Type: GrantFiled: December 2, 2008Date of Patent: August 9, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Shigeki Komori, Toshiyuki Isa, Ryu Komatsu
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Patent number: 7985605Abstract: A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order (a thin-film stacked body); first etching is performed to expose the first conductive film and form at least a pattern of the thin-film stacked body; second etching is performed to form a pattern of the first conductive film. The second etching is performed under a condition in which the first conductive film is side-etched. Further, after forming the patterns, an EL layer can be formed selectively by utilizing a depression and a projection due to the patterns.Type: GrantFiled: April 13, 2009Date of Patent: July 26, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shigeki Komori, Ryu Komatsu
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Patent number: 7985604Abstract: A photoelectric conversion device having an excellent photoelectric conversion characteristic is provided while effectively utilizing limited resources. A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer, a first electrode, and an insulating layer are formed on the one surface side of the single crystal semiconductor substrate. After bonding the insulating layer to a supporting substrate, the single crystal semiconductor substrate is separated with the fragile layer or its vicinity used as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate.Type: GrantFiled: November 26, 2008Date of Patent: July 26, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Fumito Isaka, Sho Kato, Kosei Nei, Ryu Komatsu, Akihisa Shimomura, Koji Dairiki
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Publication number: 20110156042Abstract: A thin film transistor is provided with a high crystallized region in a channel formation region and a high resistance region between a source and a drain, and thus has a high electric effect mobility and a large on current. The thin film transistor includes an “impurity which suppresses generation of crystal nuclei” contained in the base layer or located on its surface, a first wiring layer over a base layer, an impurity semiconductor layer over the first wiring, a semiconductor layer over the impurity semiconductor layer, the semiconductor layer comprises a crystalline region and a region containing an amorphous phase which is formed adjacent to the base layer.Type: ApplicationFiled: December 23, 2010Publication date: June 30, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu MIYAIRI, Ryu KOMATSU, Takafumi MIZOGUCHI
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Patent number: 7939426Abstract: An SOI substrate is manufactured by a method in which a first insulating film is formed over a first substrate over which a plurality of first single crystal semiconductor films is formed; the first insulating film is planarized; heat treatment is performed on a single crystal semiconductor substrate attached to the first insulating film; a second single crystal semiconductor film is formed; a third single crystal semiconductor film is formed using the first single crystal semiconductor films and the second single crystal semiconductor films as seed layers; a fragile layer is formed by introducing ions into the third single crystal semiconductor film; a second insulating film is formed over the third single crystal semiconductor film; heat treatment is performed on a second substrate superposed on the second insulating film; and a part of the third single crystal semiconductor film is fixed to the second substrate.Type: GrantFiled: July 28, 2010Date of Patent: May 10, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Fumito Isaka, Sho Kato, Kosei Nei, Ryu Komatsu, Tatsuya Mizoi, Akihisa Shimomura
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Publication number: 20100291755Abstract: An SOI substrate is manufactured by a method in which a first insulating film is formed over a first substrate over which a plurality of first single crystal semiconductor films is formed; the first insulating film is planarized; heat treatment is performed on a single crystal semiconductor substrate attached to the first insulating film; a second single crystal semiconductor film is formed; a third single crystal semiconductor film is formed using the first single crystal semiconductor films and the second single crystal semiconductor films as seed layers; a fragile layer is formed by introducing ions into the third single crystal semiconductor film; a second insulating film is formed over the third single crystal semiconductor film; heat treatment is performed on a second substrate superposed on the second insulating film; and a part of the third single crystal semiconductor film is fixed to the second substrate.Type: ApplicationFiled: July 28, 2010Publication date: November 18, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Fumito ISAKA, Sho KATO, Kosei NEI, Ryu KOMATSU, Tatsuya MIZOI, Akihisa SHIMOMURA
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Patent number: 7790483Abstract: To provide a manufacturing method of a thin film transistor and a display device with fewer masks than a conventional method. A thin film transistor is manufactured by including the steps of: forming a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film to be stacked; forming a resist mask including three regions with different thicknesses; performing first etching to form a thin-film stack body; performing second etching in which side-etching is performed on the thin-film stack body to form a gate electrode layer; and recessing the resist mask to form a semiconductor layer and a source and drain electrode layer. A resist mask including three regions with different thicknesses can be formed using a four-tone photomask, for example.Type: GrantFiled: May 28, 2009Date of Patent: September 7, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Ryu Komatsu
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Patent number: 7781308Abstract: A second single crystal semiconductor film is formed over a first single crystal semiconductor film; a separation layer is formed by addition of ions into the second single crystal semiconductor film; a second insulating film functioning as a bonding layer is formed over the second single crystal semiconductor film; a surface of a first SOI substrate and a surface of a second substrate are made to face each other, so that a surface of the second insulating film and the surface of the second substrate are bonded to each other; and then heat treatment is performed to cause cleavage at the separation layer, so that a second SOI substrate in which a part of the second single crystal semiconductor film is provided over the second substrate with the second insulating film interposed therebetween is formed.Type: GrantFiled: November 25, 2008Date of Patent: August 24, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Fumito Isaka, Sho Kato, Ryu Komatsu, Kosei Nei, Akihisa Shimomura
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Patent number: 7767547Abstract: An SOI substrate is manufactured by a method in which a first insulating film is formed over a first substrate over which a plurality of first single crystal semiconductor films is formed; the first insulating film is planarized; heat treatment is performed on a single crystal semiconductor substrate attached to the first insulating film; a second single crystal semiconductor film is formed; a third single crystal semiconductor film is formed using the first single crystal semiconductor films and the second single crystal semiconductor films as seed layers; a fragile layer is formed by introducing ions into the third single crystal semiconductor film; a second insulating film is formed over the third single crystal semiconductor film; heat treatment is performed on a second substrate superposed on the second insulating film; and a part of the third single crystal semiconductor film is fixed to the second substrate.Type: GrantFiled: January 27, 2009Date of Patent: August 3, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventors: Fumito Isaka, Sho Kato, Kosei Nei, Ryu Komatsu, Tatsuya Mizoi, Akihisa Shimomura
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Publication number: 20090311809Abstract: To provide a manufacturing method of a thin film transistor and a display device with fewer masks than a conventional method. A thin film transistor is manufactured by including the steps of: forming a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film to be stacked; forming a resist mask including three regions with different thicknesses; performing first etching to form a thin-film stack body; performing second etching in which side-etching is performed on the thin-film stack body to form a gate electrode layer; and recessing the resist mask to form a semiconductor layer and a source and drain electrode layer. A resist mask including three regions with different thicknesses can be formed using a four-tone photomask, for example.Type: ApplicationFiled: May 28, 2009Publication date: December 17, 2009Applicant: SEMICONDUCTOR ENERY LABORATORY CO., LTD.Inventors: Hidekazu Miyairi, Ryu Komatsu
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Publication number: 20090261369Abstract: A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order (a thin-film stacked body); first etching is performed to expose the first conductive film and form at least a pattern of the thin-film stacked body; second etching is performed to form a pattern of the first conductive film. The second etching is performed under a condition in which the first conductive film is side-etched. Further, after forming the patterns, an EL layer can be formed selectively by utilizing a depression and a projection due to the patterns.Type: ApplicationFiled: April 13, 2009Publication date: October 22, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shigeki KOMORI, Ryu KOMATSU
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Publication number: 20090197392Abstract: An SOI substrate is manufactured by a method in which a first insulating film is formed over a first substrate over which a plurality of first single crystal semiconductor films is formed; the first insulating film is planarized; heat treatment is performed on a single crystal semiconductor substrate attached to the first insulating film; a second single crystal semiconductor film is formed; a third single crystal semiconductor film is formed using the first single crystal semiconductor films and the second single crystal semiconductor films as seed layers; a fragile layer is formed by introducing ions into the third single crystal semiconductor film; a second insulating film is formed over the third single crystal semiconductor film; heat treatment is performed on a second substrate superposed on the second insulating film; and a part of the third single crystal semiconductor film is fixed to the second substrate.Type: ApplicationFiled: January 27, 2009Publication date: August 6, 2009Inventors: Fumito ISAKA, Sho KATO, Kosei NEI, Ryu KOMATSU, Tatsuya MIZOI, Akihisa SHIMOMURA
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Publication number: 20090152559Abstract: A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.Type: ApplicationFiled: December 2, 2008Publication date: June 18, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu Miyairi, Shigeki Komori, Toshiyuki Isa, Ryu Komatsu