Patents by Inventor Ryuji Ueno

Ryuji Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230330209
    Abstract: The present disclosure provides a method for treating an inflammatory condition, especially an age related inflammatory condition in a mammalian subject in need thereof, which comprises an effective amount of a virus like particle comprising a viral structural protein and a galectin-3 antigen, a composition or vaccine comprising for the purpose thereof.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 19, 2023
    Applicants: CYN-K, LLC, Kyoto University
    Inventors: Ryuji Ueno, Wataru Akahata, Kazuya Goto
  • Patent number: 11462634
    Abstract: An object of the present invention is to provide a semiconductor device capable of reducing the on-voltage and a manufacturing method thereof. According to the present invention, a semiconductor device includes a Si substrate, a p-type anode layer provided on the front surface of the Si substrate, an anode electrode provided on the p-type anode layer, an n-type cathode layer and a p-type cathode layer provided adjacent to each other on a back surface of the Si substrate, an Al alloy layer provided on the n-type cathode layer and containing Si, and an Al alloy layer provided on the p-type cathode layer and containing Si, in which impurity concentration in the n-type cathode layer is 1E19 cm?3 or higher and impurity concentration in the p-type cathode layer is 10% or lower of the impurity concentration in the n-type cathode layer.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 4, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Tanaka, Ryuji Ueno, Masahiro Ujike
  • Patent number: 11380585
    Abstract: A semiconductor device manufacturing method includes thinning a wafer to form a wafer having an annular protruding portion on a peripheral portion thereof by grinding a central portion of a back surface of the wafer and then performing wet etching on the back surface of the wafer, forming a backside electrode on the back surface of the wafer, performing plating to evenly form a metal film on a portion of the backside electrode on the annular protruding portion, attaching a dicing tape to the metal film, and dicing the wafer having the dicing tape attached thereto.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 5, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryuji Ueno, Masatoshi Sunamoto
  • Patent number: 11345726
    Abstract: The present invention provides a particle comprising a polypeptide and at least one antigen, and a composition comprising thereof.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: May 31, 2022
    Assignee: VLP Theranentics. Inc.
    Inventors: Ryuji Ueno, Wataru Akahata
  • Patent number: 11335595
    Abstract: Provided is a semiconductor element including: a front-back conduction-type substrate including a front-side electrode and a back-side electrode; and an electroless plating layer formed on at least one of the electrodes of the front-back conduction-type substrate. The electroless plating layer includes: an electroless nickel-phosphorus plating layer; and an electroless gold plating layer formed on the electroless nickel-phosphorus plating layer, and has a plurality of recesses formed on a surface thereof to be joined with solder.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: May 17, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masatoshi Sunamoto, Ryuji Ueno
  • Publication number: 20220049357
    Abstract: Provided is a semiconductor device, including: a front-back conduction-type semiconductor element; a front-side electrode formed on the front-back conduction-type semiconductor element; an electroless nickel-containing plating layer formed on the front-side electrode; and an electroless gold plating layer formed on the electroless nickel-containing plating layer, wherein the semiconductor device has a low-nickel concentration layer on a side of the electroless nickel-containing plating layer in contact with the electroless gold plating layer, and wherein the low-nickel concentration layer has a thickness smaller than that of the electroless gold plating layer.
    Type: Application
    Filed: March 12, 2020
    Publication date: February 17, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masatoshi SUNAMOTO, Ryuji UENO, Misako KAWASUMI
  • Publication number: 20220002682
    Abstract: Provided is an alphavirus replicon particle (ARP), which comprises (i) alphavirus structural proteins comprising capsid and/or envelope, and (ii) an alphavirus replicon comprising a polynucleotide encoding alphavirus non-structural proteins nsp1, nsp2, nsp3 and nsp4 and at least one gene of interest wherein at least one of capsid, and E3 and E2 in the envelope comprise one or more amino acid alteration but E1 in the envelope comprises no amino acid alteration.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 6, 2022
    Applicant: VLP Therapeutics, Inc.
    Inventors: Wataru AKAHATA, Ryuji UENO
  • Publication number: 20210322541
    Abstract: Provided herein is an isolated polynucleotide, which encodes alphavirus non-structural proteins nsp1, nsp2, nsp3 and nsp4 and a polypeptide comprising a coronavirus protein fused to a signal sequence and/or transmembrane domain. The coronavirus protein may be the receptor binding domain of the S1 subunit of coronavirus spike (S) protein. The polynucleotide such as RNA is useful for as a vaccine against coronavirus infection, especially, COVID-19 infection.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 21, 2021
    Applicant: VLP Therapeutics, Inc.
    Inventors: Wataru AKAHATA, Jonathan F. SMITH, Ryuji UENO
  • Publication number: 20210143269
    Abstract: An object of the present invention is to provide a semiconductor device capable of reducing the on-voltage and a manufacturing method thereof. According to the present invention, a semiconductor device includes a Si substrate, a p-type anode layer provided on the front surface of the Si substrate, an anode electrode provided on the p-type anode layer, an n-type cathode layer and a p-type cathode layer provided adjacent to each other on a back surface of the Si substrate, an Al alloy layer provided on the n-type cathode layer and containing Si, and an Al alloy layer provided on the p-type cathode layer and containing Si, in which impurity concentration in the n-type cathode layer is 1E19 cm?3 or higher and impurity concentration in the p-type cathode layer is 10% or lower of the impurity concentration in the n-type cathode layer.
    Type: Application
    Filed: August 11, 2020
    Publication date: May 13, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Koji TANAKA, Ryuji UENO, Masahiro UJIKE
  • Patent number: 10937657
    Abstract: A technology capable of reducing contamination of a semiconductor substrate above which a nickel film is disposed is provided. A semiconductor device includes: a semiconductor substrate; an aluminum alloy film disposed on at least one of a front surface and a back surface of the semiconductor substrate; a catalyst metal film disposed above the aluminum alloy film and exhibiting catalytic activity for autocatalytic reaction that deposits nickel; an electroless nickel plating film disposed on the catalyst metal film; and a reactant layer disposed between the aluminum alloy film and the catalyst metal film and containing metal of the catalyst metal film.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: March 2, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryuji Ueno, Masatoshi Sunamoto
  • Patent number: 10672635
    Abstract: Provided is a semiconductor-manufacturing apparatus that forms a plated film having a highly homogeneous thickness on a target surface of a semiconductor wafer through electroless plating. A semiconductor-manufacturing apparatus forms plated films on target surfaces of a plurality of wafers held by a carrier capable of holding the wafers. The semiconductor-manufacturing apparatus includes the following: a rectification mechanism including a rectification plate having a plurality of through-holes, the rectification mechanism being held by the carrier in such a manner that the rectification plate faces the target surface of each wafer; a bath in which a chemical solution for forming each plated film is stored, and in which the carrier, holding the plurality of wafers and the rectification mechanism, is immersed in the chemical solution; and a driver configured to shake the carrier as immersed in the bath with a relative positional relationship between each wafer and the through-holes kept constant.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 2, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryuji Ueno, Masatoshi Sunamoto
  • Patent number: 10561649
    Abstract: Provided is a method for treating a condition or disease which is one of the indications for opioid use, which comprises administering a combination of: (a) a pharmaceutically effective amount of an opioid, and (b) a pharmaceutically effective amount of a prostaglandin (PG) compound represented by the formula (I): to a patient in need thereof.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: February 18, 2020
    Assignee: SUCAMPO AG
    Inventor: Ryuji Ueno
  • Publication number: 20190393173
    Abstract: Provided is a semiconductor element including: a front-back conduction-type substrate including a front-side electrode and a back-side electrode; and an electroless plating layer formed on at least one of the electrodes of the front-back conduction-type substrate. The electroless plating layer includes: an electroless nickel-phosphorus plating layer; and an electroless gold plating layer formed on the electroless nickel-phosphorus plating layer, and has a plurality of recesses formed on a surface thereof to be joined with solder.
    Type: Application
    Filed: February 7, 2018
    Publication date: December 26, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masatoshi SUNAMOTO, Ryuji UENO
  • Publication number: 20190351041
    Abstract: The present invention provides a particle comprising a polypeptide and at least one malaria antigen, and a composition or vaccine comprising thereof, its use in medicine, particularly in the prevention or treatment of malaria infections.
    Type: Application
    Filed: March 28, 2019
    Publication date: November 21, 2019
    Applicant: VLP Therapeutics, LLC
    Inventors: Ryuji UENO, Wataru AKAHATA
  • Patent number: 10464986
    Abstract: The present invention provides a virus like particle comprising a virus structural protein and an antigen derived from PD-1 or a ligand of PD-1, and a composition or kit comprising thereof, its use in immune response etc.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 5, 2019
    Assignee: VLP Therapeutics, LLC
    Inventors: Wataru Akahata, Ryuji Ueno
  • Publication number: 20190267256
    Abstract: Provided is a semiconductor-manufacturing apparatus that forms a plated film having a highly homogeneous thickness on a target surface of a semiconductor wafer through electroless plating. A semiconductor-manufacturing apparatus forms plated films on target surfaces of a plurality of wafers held by a carrier capable of holding the wafers. The semiconductor-manufacturing apparatus includes the following: a rectification mechanism including a rectification plate having a plurality of through-holes, the rectification mechanism being held by the carrier in such a manner that the rectification plate faces the target surface of each wafer; a bath in which a chemical solution for forming each plated film is stored, and in which the carrier, holding the plurality of wafers and the rectification mechanism, is immersed in the chemical solution; and a driver configured to shake the carrier as immersed in the bath with a relative positional relationship between each wafer and the through-holes kept constant.
    Type: Application
    Filed: December 4, 2018
    Publication date: August 29, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryuji UENO, Masatoshi SUNAMOTO
  • Patent number: 10385101
    Abstract: A virus like particle comprising a viral structural protein which comprises modified envelope protein E3. The viral structural protein may be that derived from or alphavirus or flavivirus. Especially, the viral structural protein may be derived from Chikungunya virus or Venezuelan equine encephalitis virus.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 20, 2019
    Assignee: VLP Therapeutics, LLC
    Inventors: Wataru Akahata, Ryuji Ueno
  • Publication number: 20190244819
    Abstract: A technology capable of reducing contamination of a semiconductor substrate above which a nickel film is disposed is provided. A semiconductor device includes: a semiconductor substrate; an aluminum alloy film disposed on at least one of a front surface and a back surface of the semiconductor substrate; a catalyst metal film disposed above the aluminum alloy film and exhibiting catalytic activity for autocatalytic reaction that deposits nickel; an electroless nickel plating film disposed on the catalyst metal film; and a reactant layer disposed between the aluminum alloy film and the catalyst metal film and containing metal of the catalyst metal film.
    Type: Application
    Filed: October 28, 2016
    Publication date: August 8, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryuji UENO, Masatoshi SUNAMOTO
  • Publication number: 20190185822
    Abstract: Provided is an alphavirus replicon particle (ARP), which comprises (i) alphavirus structural proteins comprising capsid and/or envelope, and (ii) an alphavirus replicon comprising a polynucleotide encoding alphavirus non-structural proteins nsp1, nsp2, nsp3 and nsp4 and at least one gene of interest wherein at least one of capsid, and E3 and E2 in the envelope comprise one or more amino acid alteration but E1 in the envelope comprises no amino acid alteration.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 20, 2019
    Applicant: VLP Therapeutics, LLC
    Inventors: Wataru Akahata, Ryuji Ueno
  • Patent number: 10262960
    Abstract: In a semiconductor element of the present invention, an electroless nickel-phosphorus plating layer and an electroless gold plating layer are formed on both a front-side electrode and a back-side electrode of a front-back conduction-type substrate. The front-side electrode and the back-side electrode are formed of aluminum or an aluminum alloy. The proportion of the thickness of the electroless nickel-phosphorus plating layer formed on the front-side electrode with respect to the thickness of the electroless nickel-phosphorus plating layer formed on the back-side electrode is in a range of 1.0 to 3.5. The semiconductor element of the present invention allows the occurrence of voids inside solder during mounting by soldering to be prevented.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 16, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masatoshi Sunamoto, Ryuji Ueno