Patents by Inventor Sameer P. Pendharkar
Sameer P. Pendharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9337106Abstract: A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.Type: GrantFiled: December 18, 2014Date of Patent: May 10, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer P. Pendharkar, Binghua Hu
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Publication number: 20160093612Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.Type: ApplicationFiled: December 10, 2015Publication date: March 31, 2016Inventors: Yongxi Zhang, Sameer P. Pendharkar
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Patent number: 9245998Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.Type: GrantFiled: December 22, 2014Date of Patent: January 26, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar
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Publication number: 20150340496Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.Type: ApplicationFiled: May 23, 2014Publication date: November 26, 2015Applicant: Texas Instruments IncorporatedInventors: YONGXI ZHANG, PHILIP L. HOWER, SAMEER P. PENDHARKAR, JOHN LIN, GURU MATHUR, SCOTT BALSTER, VICTOR SINOW
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Publication number: 20150311281Abstract: A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.Type: ApplicationFiled: November 26, 2014Publication date: October 29, 2015Applicant: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, Binghua Hu, Henry Litzmann Edwards
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Publication number: 20150187934Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.Type: ApplicationFiled: December 22, 2014Publication date: July 2, 2015Inventors: Yongxi Zhang, Sameer P. Pendharkar
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Publication number: 20150187658Abstract: A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.Type: ApplicationFiled: December 18, 2014Publication date: July 2, 2015Inventors: Sameer P. PENDHARKAR, Binghua HU
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Publication number: 20140256108Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.Type: ApplicationFiled: May 22, 2014Publication date: September 11, 2014Inventors: Sameer P. PENDHARKAR, John LIN
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Patent number: 8790981Abstract: A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.Type: GrantFiled: August 5, 2009Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: Byron Neville Burgess, Sameer P. Pendharkar
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Patent number: 8754469Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.Type: GrantFiled: October 25, 2011Date of Patent: June 17, 2014Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, John Lin
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Patent number: 8598008Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.Type: GrantFiled: October 20, 2011Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, Marie Denison, Yongxi Zhang
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Patent number: 8309423Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.Type: GrantFiled: March 1, 2012Date of Patent: November 13, 2012Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, Binghua Hu
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Patent number: 8274131Abstract: A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.Type: GrantFiled: December 7, 2010Date of Patent: September 25, 2012Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, John Lin, Philip L. Hower, Steven L. Merchant
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Patent number: 8264038Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.Type: GrantFiled: August 7, 2009Date of Patent: September 11, 2012Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, Binghua Hu, Xinfen Chen
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Patent number: 8217453Abstract: A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.Type: GrantFiled: August 7, 2009Date of Patent: July 10, 2012Assignee: Texas Instruments IncorporatedInventor: Sameer P. Pendharkar
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Publication number: 20120164814Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.Type: ApplicationFiled: March 1, 2012Publication date: June 28, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer P. PENDHARKAR, Binghua HU
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Publication number: 20120098062Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.Type: ApplicationFiled: October 25, 2011Publication date: April 26, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer P. Pendharkar, John Lin
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Publication number: 20120098098Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.Type: ApplicationFiled: October 20, 2011Publication date: April 26, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer P. Pendharkar, Marie Denison, Yongxi Zhang
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Publication number: 20120098065Abstract: An integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate. A process of forming an integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate, so that the source/drain implant is blocked from the drift region below the gap.Type: ApplicationFiled: October 25, 2011Publication date: April 26, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Sameer P. Pendharkar
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Patent number: 8154101Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.Type: GrantFiled: August 7, 2009Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, Binghua Hu