Abstract: A method of repairing a photomask with a depression defect includes providing a photomask including a depression defect on a transparent substrate, forming a protection layer which covers the depression defect, etching a predetermined depth of the transparent substrate of the photomask with the protection layer as the etch mask, and removing the protection layer and the transparent substrate under the unetched protection layer, wherein a defect free photomask is produced.

Abstract: The present invention relates to a novel protease, a polynucleotide encoding the protease, and a fibrinolytic agent comprising the same. The protease is obtained from a new gene source by using metagenomic library technology, and can replace the conventional fibrinolytic agent.

Abstract: DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions. The first and second storage nodes are laterally offset from the respective first and second source regions along the first direction.

Abstract: Methods of forming field effect transistors having buried gate electrodes include the steps of forming a semiconductor substrate having a sacrificial gate electrode buried beneath a surface of the semiconductor substrate and then removing the sacrificial gate electrode to define a gate electrode cavity beneath the surface. The gate electrode cavity is lined with a gate insulating layer. The lined gate electrode cavity is filled with a first insulated gate electrode. A second insulated gate electrode is also formed on a portion of the semiconductor substrate extending opposite the first insulated gate electrode so that a channel region of the field effect transistor extends between the first and second insulated gate electrodes. Source and drain regions are also formed adjacent opposite ends of the first and second insulated gate electrodes.

Abstract: A method of repairing a photomask with a depression defect includes providing a photomask including a depression defect on a transparent substrate, forming a protection layer which covers the depression defect, etching a predetermined depth of the transparent substrate of the photomask with the protection layer as the etch mask, and removing the protection layer and the transparent substrate under the unetched protection layer, wherein a defect tree photomask is produced.

Abstract: A semiconductor device includes an upper gate trench crossing an active region of a semiconductor substrate, a lower gate trench overlapping the upper gate trench at both ends, disposed at a lower level than the upper gate trench, and having a smaller width than the upper gate trench and wherein the lower gate trench is spaced apart from sidewalls of the upper gate trench. The semiconductor device further includes a gate pattern partially covering the bottom of the upper gate trench between the sidewall of the upper gate trench and the lower gate trench, filling the lower gate trench, and covering sidewalls of the active region adjacent to the bottom and sidewalls of the lower gate trench.

Abstract: The object of the present invention is to provide a premixed charge compression ignition (PCCI) engine. The PCCI engine has a fuel injector (22) in a suction manifold (8) to prepare a premixed charge of fuel and air and induces a natural ignition of the premixed charge in a combustion chamber (20) of a high temperature and high pressure. The PCCI engine further includes a structurally improved connecting rod which has a spring operated in organic conjunction with the other elements of the PCCI engine. The present invention further provides a PCCI reciprocating generator that is fabricated by a combination of a reciprocating generator unit with the PCCI engine, so that the PCCI reciprocating generator operates with improved operational efficiency. In the present invention, two PCCI engines may be arranged to symmetrically face each other, thus providing a multiple PCCI engine.

Abstract: DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions. The first and second storage nodes are laterally offset from the respective first and second source regions along the first direction.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Abstract: DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions. The first and second storage nodes are laterally offset from the respective first and second source regions along the first direction.

Abstract: The object of the present invention is to provide a premixed charge compression ignition (PCCI) engine. The PCCI engine has a fuel injector (22) in a suction manifold (8) to prepare a premixed charge of fuel and air and induces a natural ignition of the premixed charge in a combustion chamber (20) of a high temperature and high pressure. The PCCI engine further includes a structurally improved connecting rod which has a spring operated in organic conjunction with the other elements of the PCCI engine. The present invention further provides a PCCI reciprocating generator that is fabricated by a combination of a reciprocating generator unit with the PCCI engine, so that the PCCI reciprocating generator operates with improved operational efficiency. In the present invention, two PCCI engines may be arranged to symmetrically face each other, thus providing a multiple PCCI engine.

Abstract: Methods of forming field effect transistors having buried gate electrodes include the steps of forming a semiconductor substrate having a sacrificial gate electrode buried beneath a surface of the semiconductor substrate and then removing the sacrificial gate electrode to define a gate electrode cavity beneath the surface. The gate electrode cavity is lined with a gate insulating layer. The lined gate electrode cavity is filled with a first insulated gate electrode. A second insulated gate electrode is also formed on a portion of the semiconductor substrate extending opposite the first insulated gate electrode so that a channel region of the field effect transistor extends between the first and second insulated gate electrodes. Source and drain regions are also formed adjacent opposite ends of the first and second insulated gate electrodes.

Abstract: Methods of fabricating integrated circuit devices include forming a trench in a face of an integrated circuit substrate. The trench has a trench sidewall and a trench floor. The method further including forming a first insulating layer on the trench sidewall that exposes at least part of the trench floor and forming a conductive plug in the trench on the trench floor. The conductive plug is electrically connected to the substrate at the trench floor through the trench sidewall that exposes the at least part of the trench floor. The conductive plug also has a plug top opposite the trench floor that is recessed beneath the face of the substrate. The method further includes forming a second insulating layer on the plug top.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Abstract: An apparatus for testing a signal processor includes an integrator and a control section. The integrator switches an input signal in response to a first clock signal to allow the input signal to be charged in at least one capacitive element, and outputs the charged input signal in response to a second clock signal. The control section is coupled to the integrator, and provides the integrator with a control signal to discharge the capacitive elements based on a level of the input signal at a previous part of a test mode. The time required for testing the signal processor is reduced.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Abstract: An apparatus for testing a signal processor includes an integrator and a control section. The integrator switches an input signal in response to a first clock signal to allow the input signal to be charged in at least one capacitive element, and outputs the charged input signal in response to a second clock signal. The control section is coupled to the integrator, and provides the integrator with a control signal to discharge the capacitive elements based on a level of the input signal at a previous part of a test mode. The time required for testing the signal processor is reduced.

Abstract: Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel.

Abstract: Methods for manufacturing a storage node of a capacitor of a semiconductor device and a storage node manufactured by these methods are provided. An exemplary method for manufacturing a storage node of a capacitor of a semiconductor device includes forming a mold layer on a semiconductor substrate, forming a mold for the storage node by patterning the mold layer by a photolithography process, introducing a photomask which includes a plurality of light transmitting patterns separated from each other and which define the region to be occupied by the storage node, and forming a storage node that has the shape formed by the mold. The photolithography process is performed with the occurrence of a pattern bridge phenomenon, e.g., the transferred light transmitting patterns are connected to each other in a pattern transferred from the light transmitting patterns to the mold.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.