Abstract: The present invention relates to a negative electrode active material for an electrode mixture, and to an electrochemical cell comprising the negative electrode active material, wherein the negative electrode active material comprises an amorphous carbonaceous material and a doping element, and exhibits, in the temperature range of 450° C. to 950° C., at least two peaks of derivative weight change calculated by thermogravimetric analysis, and exhibits a maximum heat peak output of 20 mW to 60 mW as measured by differential scanning calorimetry.

Abstract: The present invention relates to an electrical safety diagnosis system and apparatus, which are configured to enable sensed data on user surroundings in a U-city environment, such as electrical safety data for switchboards and distribution boards, and water leakages, faulty outlet connections, etc., to be managed remotely by a server at a U-city integrated information center. In particular, the present invention relates to an electrical safety diagnosis system and apparatus which use a U-city integrated information network to preemptively perform checking and analyses for potential electrically-induced disasters that can occur in public facilities, stores, buildings, and homes within a U-city, by means of a U-city integrated information center, and prevent electrical fires or shocks at the electrical equipment of switchboards or distribution boards, and dangerous conditions (such as water leakages, abnormal temperatures, gas, and faulty outlet connections) in facilities used by users.

Abstract: Disclosed are a negative active material for a lithium secondary battery and a lithium secondary battery including same. The negative active material for a lithium secondary battery includes an amorphous carbon material, with a tap density of 0.7 to 1.5 g/cm3 and an angle of repose of 15 to 55 degrees.

Abstract: Disclosed herein are a CMP slurry composition with high-planarity and a CMP process for polishing a dielectric film using the same. More specifically, a CMP slurry composition with high-planarity includes a carbon compound having tens of thousands of carboxyl groups and having a molecular weight ranging from hundreds of thousands to millions, an abrasive, and water. A CMP process for polishing a dielectric film utilizes the disclosed slurry composition. The slurry composition enables complete and overall planarization of the dielectric film by polishing the part of the film having a higher step difference through CMP process. Accordingly, the disclosed slurry composition is useful for the CMP process of all semiconductor devices including those having ultrafine patterns.

Abstract: In a substrate protecting member and a method of forming an analysis sample using the same, the substrate protecting member includes a protective layer attached to a semiconductor substrate to protect a defect portion of the semiconductor substrate and a sensing line including first, second and third conductive lines located on the protective layer. The first conductive line extends in a first direction. The second conductive line extends to an edge of the protective layer in a second direction different from the first direction. The second and third conductive lines are electrically connected to first and second end portions of the first conductive line, respectively. The third conductive line extends to an edge of the protective layer in the second direction.

Abstract: The present invention relates to a high-voltage electric double layer capacitor (EDLC), and more particularly, to an EDLC in which a surge voltage and an operating voltage are enhanced by improving the structure of a unit cell. The EDLC according to the present invention includes a unit cell having at least three electrodes. According to a preferred embodiment of the present invention, the unit cell has a structure constructed by sequentially laminating a first insulating paper layer with a sheet of insulating paper, a first electrode layer with at least two electrodes, a second insulating paper layer with a sheet of insulating paper, and a second electrode layer with at least one electrode. In accordance with the present invention, the number of electrode-facing surfaces increases, and a surge voltage and an operating voltage increase in proportion to the increased number of the electrode-facing surfaces, resulting in a high energy storage density.

Abstract: Disclosed is a method for forming a polysilicon plug of a semiconductor device.

Abstract: The present invention relates to a high-voltage electric double layer capacitor (EDLC), and more particularly, to an EDLC in which a surge voltage and an operating voltage are enhanced by improving the structure of a unit cell. The EDLC according to the present invention includes a unit cell having at least three electrodes. According to a preferred embodiment of the present invention, the unit cell has a structure constructed by sequentially laminating a first insulating paper layer with a sheet of insulating paper, a first electrode layer with at least two electrodes, a second insulating paper layer with a sheet of insulating paper, and a second electrode layer with at least one electrode. In accordance with the present invention, the number of electrode-facing surfaces increases, and a surge voltage and an operating voltage increase in proportion to the increased number of the electrode-facing surfaces, resulting in a high energy storage density.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.

Abstract: An aqueous slurry composition of the present invention, comprising a first polyacrylic acid and a second polyacrylic acid having specific weight average molecular weights ranging from 1,000,000 to 3,000,000 and from 2,000,000 to 8,000,000, respectively, in combination with a metal oxide abrasive, can perform highly efficient chemical mechanical planarization (CMP) of a layer formed during the manufacturing process of a multi-layered semiconductor device.

Abstract: CMP slurries for oxide film and a method for forming a metal line contact plug of a semiconductor device are described herein. When a polishing process of a multi-layer film is performed by using the disclosed CMP slurry for oxide film including an HXOn compound (wherein n is an integer from 1 to 4), a stable landing plug poly can be formed by preventing step differences by reducing interlayer polishing speed differences.

Abstract: The present invention discloses method for manufacturing capacitor of semiconductor device wherein a bonding layer is exposed via etch-back process without using a contact hole mask. In accordance with the method of the present invention, an interlayer insulating film, a bonding layer and a hard mask layer are sequentially formed on a semiconductor substrate. The hard mask layer, the bonding layer and the interlayer insulating film are then etched to form a storage electrode contact hole. The storage electrode contact hole is partially filled to form a storage electrode contact plug and the remaining portion is filled with a barrier metal layer pattern. The hard mask layer is then removed and a storage electrode contacting the barrier metal layer pattern is then formed on the bonding layer.

Abstract: A method of forming a gate in a semiconductor device includes forming a dummy gate insulating layer on a semiconductor substrate having a field oxide layer isolating the device, depositing a dummy gate polysilicon layer and a hard mask layer on the dummy gate insulating layer sequentially, patterning the hard mask layer into a mask pattern and patterning the dummy gate polysilicon layer using the mask pattern as an etch barrier, forming spacers at both sidewalls of the dummy gate polysilicon layer, depositing an insulating interlayer on the resultant structure after forming the spacers, exposing a surface of the dummy gate polysilicon layer by carrying out an oxide layer CMP process having a high selection ratio against the dummy gate polysilicon layer, forming a damascene structure by removing the dummy gate polysilicon layer and the dummy gate insulating layer using the insulating interlayer as another etch barrier, depositing a gate insulating layer and a gate metal layer on the entire surface of the semic

Abstract: The present invention discloses method for manufacturing capacitor of semiconductor device wherein a bonding layer is exposed via etch-back process without using a contact hole mask. In accordance with the method of the present invention, an interlayer insulating film, a bonding layer and a hard mask layer are sequentially formed on a semiconductor substrate. The hard mask layer, the bonding layer and the interlayer insulating film are then etched to form a storage electrode contact hole. The storage electrode contact hole is partially filled to form a storage electrode contact plug and the remaining portion is filled with a barrier metal layer pattern. The hard mask layer is then removed and a storage electrode contacting the barrier metal layer pattern is then formed on the bonding layer.

Abstract: A CMP slurry for ruthenium and a polishing process using the same. In a process technology below 0.1 &mgr;m, when a capacitor using a (Ba1−xSrx)TiO3 film as a dielectric film is fabricated, the slurry is used to polish a ruthenium film deposited as a lower electrode according to a CMP process. The CMP process is performed by using the slurry, to improve a polishing speed of ruthenium under a low polishing pressure. In addition, the CMP process is performed according to an one-step process by using one kind of slurry. As a result, defects on an insulating film are reduced and a polishing property is improved, thereby simplifying the CMP process.

Abstract: Methods for forming capacitor of FeRAM are disclosed. The disclosed methods can prevent the step difference from an etch-back process and scratch on a Pt layer in a CMP process using a basic slurry by performing a CMP process using an acidic slurry including an organic acid when isolating a storage electrode in a formation process of a FeRAM capacitor.

Abstract: A Chemical Mechanical Polishing(abbreviated as “CMP”) slurry composition for polysilicon and method of forming a self-aligned floating gate of a flash memory device are disclosed for performing CMP process using slurry having higher polishing selectivity to polysilicon than to isolation oxide film which is an etching barrier film.

Abstract: A CMP slurry for ruthenium titanium nitride and a polishing process using the same. In a process technology below 0.1 &mgr;m, when a capacitor using a (Ba1-xSrx)TiO3 film as a dielectric film is fabricated, the slurry is used to polish a ruthenium titanium nitride film deposited as a barrier film according to a CMP process. The CMP process is performed by using the slurry, to improve a polishing speed of ruthenium titanium nitride under a low polishing pressure. In addition, the CMP process is performed according to an one-step process by using one kind of slurry. As a result, defects on an insulating film are reduced and a polishing property is improved, thereby simplifying the CMP process.

Abstract: Methods for forming capacitor of FeRAM are disclosed. The disclosed methods can prevent the step difference from an etch-back process and scratch on a Pt layer in a CMP process using a basic slurry by performing a CMP process using an acidic slurry including an organic acid when isolating a storage electrode in a formation process of a FeRAM capacitor.

Abstract: A nitride CMP slurry having selectivity to nitride over oxide. The slurry increases the polishing speed of a nitride film by varying the pH of the slurry, and polishes the nitride film faster than an oxide film by decreasing the polishing speed of the oxide film. As a result, the slurry provides a CMP process for manufacturing a high density and highly integrated semiconductor device and a structural development of new concept device.