Abstract: The present invention relates to novel mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, a novel crystalline form thereof, and a process for preparing the same. More specifically, the present invention relates to mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, which is excellent in stability, solubility, and bioavailability when it is administered not only alone but also in combination with other drugs and which has a high purity, a crystalline form thereof, and a process for preparing the same.

Abstract: An apparatus and method for treating a substrate are provided. The apparatus includes at least one first process chamber configured to supply a developer onto the substrate; at least one second process chamber configured to treat the substrate using a supercritical fluid; a transfer chamber configured to transfer the substrate from the at least one first process chamber to the at least one second process chamber, while the developer supplied in the at least one first process chamber remains on the substrate; and a temperature and humidity control system configured to manage temperature and humidity of the transfer chamber by supplying a first gas of constant temperature and humidity into the transfer chamber.

Abstract: Provided is a heavy-duty probe card transfer and loading device including a main body that moves along a set travel route, a loading arm assembly including an up-down unit coupled to the main body and configured to perform a lifting and lowering operation, a first arm drive unit rotatably coupled to the up-down unit, and a second arm drive unit rotatably coupled to the other end of the first arm drive unit, and a gripper unit rotatably coupled to the second arm drive part to grip a heavy-duty probe card and place the same on the main body.

Abstract: Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.

Abstract: Apparatuses, systems, and methods for a row decoder with multiple section enable signal voltage domains. A row address is decoded into a pre-enable signal. A first section enable signal and a second section enable signal are generated based on the pre-enable signal. The first section enable signal is in a first voltage domain where a first voltage represents an logical high, the second section enable signal is in a second voltage domain where a second voltage represents a logical high, and the pre-enable signal is in a third voltage domain where a third voltage represents a logical high. The second voltage is between the first and third voltages. A word line driver signal is generated based on the first and the second section enable signals.

Abstract: The present invention relates to the present invention provides novel recombinant protein produced from cholinesterase gene derived from Pseudomonas aeruginosa and the composition comprising the same for treating or preventing a neurological disease.

Abstract: Bit line equalization driver circuits and related apparatuses, methods, and computing systems are disclosed. An apparatus includes an output inverter including a pull-up transistor and a pull-down transistor electrically connected in series between a pull-up node and a pull-down node. An output node is electrically connected between the pull-up transistor and the pull-down transistor. The pull-down transistor includes a short length transistor having a degradation voltage potential across the pull-down transistor below which the pull-down transistor is configured to operate to avoid degradation of the pull-down transistor. The apparatus also includes biasing circuitry configured to control voltage potentials at the pull-up node and the pull-down node to enable the output inverter to assert, at the output node, an output voltage potential that is greater than the degradation voltage potential higher than a low power supply voltage potential at the low power supply node.

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

Abstract: Bit line equalization driver circuits and related apparatuses, methods, and computing systems are disclosed. An apparatus includes an output inverter including a pull-up transistor and a pull-down transistor electrically connected in series between a pull-up node and a pull-down node. An output node is electrically connected between the pull-up transistor and the pull-down transistor. The pull-down transistor includes a short length transistor having a degradation voltage potential across the pull-down transistor below which the pull-down transistor is configured to operate to avoid degradation of the pull-down transistor. The apparatus also includes biasing circuitry configured to control voltage potentials at the pull-up node and the pull-down node to enable the output inverter to assert, at the output node, an output voltage potential that is greater than the degradation voltage potential higher than a low power supply voltage potential at the low power supply node.

Abstract: A main word driver may be coupled to a subword driver to drive a main word line to select the subword driver. The main word driver may include a first transistor having a body and source/drain both coupled to a well. The main word driver may include a well control circuit configured to bias the well. In some examples, the well control circuit may provide a first low potential to the well followed by a second low potential lower than the first potential responsive to a precharge command. The main word driver may include a second transistor coupled to the well control circuit to receive the first and second low potentials and couple the first and second low potentials to the main word line. The body of the second transistor may be coupled to the well. Additional transistors in the main word driver may also be coupled to the well.

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier with a sensing circuit configured to precharge a connected extended digit line. A balancing circuit may be connected to the extended digit line opposite the sensing circuit. The balancing circuit may be configured to selectively connect the extended digit line to a precharging source to precharge the extended digit line.

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

Abstract: A main word driver may be coupled to a subword driver to drive a main word line to select the subword driver. The main word driver may include a first transistor having a body and source/drain both coupled to a well. The main word driver may include a well control circuit configured to bias the well. In some examples, the well control circuit may provide a first low potential to the well followed by a second low potential lower than the first potential responsive to a precharge command. The main word driver may include a second transistor coupled to the well control circuit to receive the first and second low potentials and couple the first and second low potentials to the main word line. The body of the second transistor may be coupled to the well. Additional transistors in the main word driver may also be coupled to the well.

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier with a sensing circuit configured to precharge a connected extended digit line. A balancing circuit may be connected to the extended digit line opposite the sensing circuit. The balancing circuit may be configured to selectively connect the extended digit line to a precharging source to precharge the extended digit line.

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.