Patents by Inventor Sanroku Tsukamoto
Sanroku Tsukamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11715003Abstract: An optimization apparatus calculates a first portion, among energy change caused by change in value of a neuron of a neuron group, caused by influence of another neuron of the neuron group, determines whether to allow updating the value, based on a sum of the first and second portions of the energy change, and repeats a process of updating or maintaining the value according to the determination. An arithmetic processing apparatus calculates the second portion caused by influence of a neuron not belonging to the neuron group and an initial value of the sum. A control apparatus transmits data for calculating the second portion and the initial value to the arithmetic processing apparatus, and the initial value and data for calculating the first portion to the optimization apparatus, and receives the initial value from the arithmetic processing apparatus, and a value of the neuron group from the optimization apparatus.Type: GrantFiled: February 4, 2019Date of Patent: August 1, 2023Assignee: FUJITSU LIMITEDInventors: Sanroku Tsukamoto, Satoshi Matsubara, Hirotaka Tamura
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Patent number: 11599073Abstract: A problem is inputted into an operation unit. A computation unit searches for a ground state of an Ising model. A management unit converts the problem inputted from the operation unit to the Ising model, inputs the Ising model produced by conversion and initial operating conditions into the computation unit, and has the computation unit search for the ground state using overall operating conditions produced by changing the initial operating conditions based on a result of the computation unit searching for the ground state using the initial operating conditions.Type: GrantFiled: February 25, 2019Date of Patent: March 7, 2023Assignee: FUJITSU LIMITEDInventors: Jumpei Koyama, Kazuya Takemoto, Motomu Takatsu, Satoshi Matsubara, Takayuki Shibasaki, Noboru Yoneoka, Toshiyuki Miyazawa, Akihiko Ohwada, Sanroku Tsukamoto
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Patent number: 11526740Abstract: An optimization method includes holding combining destination information indicating a combining destination neuron to be combined with a target neuron which is one of a plurality of neurons corresponding to a plurality of spins of an Ising model obtained by converting an optimization problem, the target neuron being different in a plurality of neuron circuits; holding a weighting coefficient indicating a strength of combining between the target neuron and the combining destination neuron, and outputting the weighting coefficient corresponding to the combining destination information; permitting an update of a value of the target neuron by using the weighting coefficient output and the value of the update target neuron, and outputting a determination result indicating whether or not the value of the target neuron is permitted to be updated; and determining the update target neuron based on the plurality of determination results respectively output and outputting the update target information.Type: GrantFiled: May 15, 2020Date of Patent: December 13, 2022Assignee: Fujitsu LimitedInventors: Sanroku Tsukamoto, Hirotaka Tamura, Satoshi Matsubara
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Patent number: 11521049Abstract: An optimization device includes: processing circuits each configured to: hold a first value of a neuron of an Ising model; and perform a process to determine whether to permit updating of the first value based on information of the Ising model and information about a target neuron; a control circuit configured to: set, while causing a portion of the processing circuits to perform the process for a partial neuron group, information to be used for the process for a first neuron other than the partial neuron group in a first processing circuit; cause a second processing circuit among the portion of the processing circuits to inactivate the process; and cause the first processing circuit to start the process for the first neuron; and an update neuron selection circuit configured to: select the target neuron from one or more update permissible neurons; and update the value of the target neuron.Type: GrantFiled: September 27, 2019Date of Patent: December 6, 2022Assignee: FUJITSU LIMITEDInventors: Sanroku Tsukamoto, Satoshi Matsubara
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Patent number: 11275995Abstract: An individual ising device connected to common buses includes neuron circuits, a memory, and a router. The memory holds connection destination information per neuron circuit. An individual item of connection destination information includes first address information identifying one of a plurality of connection destination neuron circuits of a neuron circuit and second address information identifying a first ising device including at least one of the connection destination neuron circuits, the first and second address information being correlated.Type: GrantFiled: May 31, 2017Date of Patent: March 15, 2022Assignee: FUJITSU LIMITEDInventors: Sanroku Tsukamoto, Hirotaka Tamura, Satoshi Matsubara
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Patent number: 11074493Abstract: Boltzmann machine includes a plurality of circuit units each having an adder that adds weighted input signals and a comparison unit that compares an output signal of the adder with a threshold signal to output a binary output signal; and digital arithmetic units each generating the weighted input signals by weighting the binary output signal of the circuit units with a weight. The comparison unit has a first comparator that compares a thermal noise with a reference voltage to output a binary digital random signal, a DA converter that converts the digital random signal to an analog random signal and varies a magnitude of the analog random signal, and a second comparator that compares the output signal of the adder with the analog random signal to generate the binary output signal with a predetermined probability function.Type: GrantFiled: January 30, 2017Date of Patent: July 27, 2021Assignee: FUJITSU LIMITEDInventors: Takumi Danjo, Sanroku Tsukamoto, Hirotaka Tamura
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Patent number: 10970361Abstract: Arithmetic circuits calculate d?1 energy values (hi2 to hid) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.Type: GrantFiled: June 7, 2017Date of Patent: April 6, 2021Assignee: FUJITSU LIMITEDInventors: David Thach, Hirotaka Tamura, Sanroku Tsukamoto
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Publication number: 20200380346Abstract: An optimization method includes holding combining destination information indicating a combining destination neuron to be combined with a target neuron which is one of a plurality of neurons corresponding to a plurality of spins of an Ising model obtained by converting an optimization problem, the target neuron being different in a plurality of neuron circuits; holding a weighting coefficient indicating a strength of combining between the target neuron and the combining destination neuron, and outputting the weighting coefficient corresponding to the combining destination information; permitting an update of a value of the target neuron by using the weighting coefficient output and the value of the update target neuron, and outputting a determination result indicating whether or not the value of the target neuron is permitted to be updated; and determining the update target neuron based on the plurality of determination results respectively output and outputting the update target information.Type: ApplicationFiled: May 15, 2020Publication date: December 3, 2020Applicant: FUJITSU LIMITEDInventors: Sanroku Tsukamoto, Hirotaka TAMURA, SATOSHI MATSUBARA
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Patent number: 10718811Abstract: A jitter measurement circuit includes an addition circuit to add a digital rectangular signal to an adjustment signal generated by a circuit that generates a first error signal based on a phase difference between a first clock signal or a data signal on which the first clock signal is superimposed and a second clock signal and generates the adjustment signal by filtering the first error signal, and a calculation circuit to calculate a first correlation value for representing an autocorrelation of the first error signal when the rectangular signal is not added to the adjustment signal, and a second correlation value for representing the autocorrelation when the rectangular signal is added to the adjustment signal, based on the first error signal and a second error signal obtained by delaying the first error signal by a variable delay amount, and output the first correlation value and the second correlation value.Type: GrantFiled: April 24, 2018Date of Patent: July 21, 2020Assignee: FUJITSU LIMITEDInventors: Joshua Liang, Ali Sheikholeslami, Sanroku Tsukamoto, Hirotaka Tamura, Hisakatsu Yamaguchi
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Publication number: 20200167635Abstract: An optimization device includes: processing circuits each configured to: hold a first value of a neuron of an Ising model; and perform a process to determine whether to permit updating of the first value based on information of the Ising model and information about a target neuron; a control circuit configured to: set, while causing a portion of the processing circuits to perform the process for a partial neuron group, information to be used for the process for a first neuron other than the partial neuron group in a first processing circuit; cause a second processing circuit among the portion of the processing circuits to inactivate the process; and cause the first processing circuit to start the process for the first neuron; and an update neuron selection circuit configured to: select the target neuron from one or more update permissible neurons; and update the value of the target neuron.Type: ApplicationFiled: September 27, 2019Publication date: May 28, 2020Applicant: FUJITSU LIMITEDInventors: Sanroku Tsukamoto, SATOSHI MATSUBARA
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Publication number: 20190286077Abstract: A problem is inputted into an operation unit. A computation unit searches for a ground state of an Ising model. A management unit converts the problem inputted from the operation unit to the Ising model, inputs the Ising model produced by conversion and initial operating conditions into the computation unit, and has the computation unit search for the ground state using overall operating conditions produced by changing the initial operating conditions based on a result of the computation unit searching for the ground state using the initial operating conditions.Type: ApplicationFiled: February 25, 2019Publication date: September 19, 2019Applicant: FUJITSU LIMITEDInventors: Jumpei KOYAMA, Kazuya TAKEMOTO, Motomu TAKATSU, Satoshi MATSUBARA, Takayuki SHIBASAKI, Noboru YONEOKA, Toshiyuki MIYAZAWA, Akihiko OHWADA, Sanroku TSUKAMOTO
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Publication number: 20190244098Abstract: An optimization apparatus calculates a first portion, among energy change caused by change in value of a neuron of a neuron group, caused by influence of another neuron of the neuron group, determines whether to allow updating the value, based on a sum of the first and second portions of the energy change, and repeats a process of updating or maintaining the value according to the determination. An arithmetic processing apparatus calculates the second portion caused by influence of a neuron not belonging to the neuron group and an initial value of the sum. A control apparatus transmits data for calculating the second portion and the initial value to the arithmetic processing apparatus, and the initial value and data for calculating the first portion to the optimization apparatus, and receives the initial value from the arithmetic processing apparatus, and a value of the neuron group from the optimization apparatus.Type: ApplicationFiled: February 4, 2019Publication date: August 8, 2019Applicant: FUJITSU LIMITEDInventors: Sanroku TSUKAMOTO, SATOSHI MATSUBARA, Hirotaka TAMURA
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Publication number: 20180313895Abstract: A jitter measurement circuit includes an addition circuit to add a digital rectangular signal to an adjustment signal generated by a circuit that generates a first error signal based on a phase difference between a first clock signal or a data signal on which the first clock signal is superimposed and a second clock signal and generates the adjustment signal by filtering the first error signal, and a calculation circuit to calculate a first correlation value for representing an autocorrelation of the first error signal when the rectangular signal is not added to the adjustment signal, and a second correlation value for representing the autocorrelation when the rectangular signal is added to the adjustment signal, based on the first error signal and a second error signal obtained by delaying the first error signal by a variable delay amount, and output the first correlation value and the second correlation value.Type: ApplicationFiled: April 24, 2018Publication date: November 1, 2018Applicant: FUJITSU LIMITEDInventors: Joshua Liang, Ali Sheikholeslami, Sanroku Tsukamoto, Hirotaka TAMURA, Hisakatsu Yamaguchi
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Patent number: 10007877Abstract: A Boltzmann machine circuit includes: a plurality of circuits each circuit configured to add one or more first values based on one or more outputs of one or more circuits which are included in the plurality of circuits and are other than the circuit and convert an addition result into an analog signal, compare the analog signal with a second value, and output a comparison result; a plurality of arithmetic circuits configured to multiply the respective comparison results by respective weight values and generate the first values; and a control circuit configured to amplify an amplitude of the analog signal generated by each of the plurality of circuits.Type: GrantFiled: April 15, 2016Date of Patent: June 26, 2018Assignee: FUJITSU LIMITEDInventors: Yanfei Chen, Sanroku Tsukamoto, Hirotaka Tamura
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Publication number: 20180018563Abstract: An individual ising device connected to common buses includes neuron circuits, a memory, and a router. The memory holds connection destination information per neuron circuit. An individual item of connection destination information includes first address information identifying one of a plurality of connection destination neuron circuits of a neuron circuit and second address information identifying a first ising device including at least one of the connection destination neuron circuits, the first and second address information being correlated.Type: ApplicationFiled: May 31, 2017Publication date: January 18, 2018Applicant: FUJITSU LIMITEDInventors: Sanroku Tsukamoto, Hirotaka TAMURA, SATOSHI MATSUBARA
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Publication number: 20170368682Abstract: A neural network apparatus includes: a plurality of neuron units each including: an adder that performs addition processing and one or more digital analog converters that perform digital-analog conversion processing, relating to weighted inputs; and a delta-sigma analog digital converter that converts an analog signal indicating an added value obtained by adding all of the weighted inputs obtained from the adder and the one or more digital analog converters, into a pulse signal according to an amplitude, and outputs the pulse signal; a plurality of arithmetic units each of which multiplies the pulse signal outputted from one neuron unit by a weighted value, and outputs a result to another neuron unit; and an oscillator that is capable of changing a frequency of a clock signal to be outputted and supplies the clock signal to the neuron unit and the arithmetic unit according to control from a control unit.Type: ApplicationFiled: May 26, 2017Publication date: December 28, 2017Applicant: FUJITSU LIMITEDInventors: Takumi Danjo, Hirotaka TAMURA, Sanroku Tsukamoto
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Publication number: 20170364477Abstract: Arithmetic circuits calculate d?1 energy values (hi2 to hid) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.Type: ApplicationFiled: June 7, 2017Publication date: December 21, 2017Applicant: FUJITSU LIMITEDInventors: David Thach, Hirotaka TAMURA, Sanroku Tsukamoto
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Publication number: 20170220924Abstract: Boltzmann machine includes a plurality of circuit units each having an adder that adds weighted input signals and a comparison unit that compares an output signal of the adder with a threshold signal to output a binary output signal; and digital arithmetic units each generating the weighted input signals by weighting the binary output signal of the circuit units with a weight. The comparison unit has a first comparator that compares a thermal noise with a reference voltage to output a binary digital random signal, a DA converter that converts the digital random signal to an analog random signal and varies a magnitude of the analog random signal, and a second comparator that compares the output signal of the adder with the analog random signal to generate the binary output signal with a predetermined probability function.Type: ApplicationFiled: January 30, 2017Publication date: August 3, 2017Applicant: FUJITSU LIMITEDInventors: Takumi DANJO, Sanroku TSUKAMOTO, Hirotaka TAMURA
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Publication number: 20170004398Abstract: A Boltzmann machine circuit includes: a plurality of circuits each circuit configured to add one or more first values based on one or more outputs of one or more circuits which are included in the plurality of circuits and are other than the circuit and convert an addition result into an analog signal, compare the analog signal with a second value, and output a comparison result; a plurality of arithmetic circuits configured to multiply the respective comparison results by respective weight values and generate the first values; and a control circuit configured to amplify an amplitude of the analog signal generated by each of the plurality of circuits.Type: ApplicationFiled: April 15, 2016Publication date: January 5, 2017Applicant: FUJITSU LIMITEDInventors: YANFEI CHEN, Sanroku Tsukamoto, Hirotaka TAMURA
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Patent number: 9509327Abstract: An A/D converter includes an A/D conversion unit, a histogram generation-storage unit, and a control unit. The A/D conversion unit is configured to receive an input voltage, perform an analog-to-digital conversion, and output digital data, and the histogram generation-storage unit is configured to receive the digital data, generate a histogram for a waveform of the input voltage, and store the generated histogram therein. The control unit is configured to control an analog-to-digital conversion characteristics of the A/D conversion unit, based on the histogram stored in the histogram generation-storage unit.Type: GrantFiled: February 16, 2016Date of Patent: November 29, 2016Assignee: FUJITSU LIMITEDInventors: Masaya Kibune, Sanroku Tsukamoto