Abstract: An A/D converter includes an A/D conversion unit, a histogram generation-storage unit, and a control unit. The A/D conversion unit is configured to receive an input voltage, perform an analog-to-digital conversion, and output digital data, and the histogram generation-storage unit is configured to receive the digital data, generate a histogram for a waveform of the input voltage, and store the generated histogram therein. The control unit is configured to control an analog-to-digital conversion characteristics of the A/D conversion unit, based on the histogram stored in the histogram generation-storage unit.

Abstract: An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together.

Abstract: There is provided a receiving device includes: a plurality of interpolation unit circuits, each interpolation unit circuit configured to perform interpolation processing of a sampling value obtained by asynchronously sampling input data, based on an interpolation ratio, so that sampling data synchronous with the input data and continuous in time is generated, wherein one of the interpolation unit circuits is provided in parallel with another of the interpolation unit circuits for a channel previous to a channel in which switching of the interpolation ratio is performed.

Abstract: There is provided a receiving device includes: a plurality of interpolation unit circuits, each interpolation unit circuit configured to perform interpolation processing of a sampling value obtained by asynchronously sampling input data, based on an interpolation ratio, so that sampling data synchronous with the input data and continuous in time is generated, wherein one of the interpolation unit circuits is provided in parallel with another of the interpolation unit circuits for a channel previous to a channel in which switching of the interpolation ratio is performed.

Abstract: An electronic circuit includes: a weighting circuit configured to generate a first current by weighting and combining a first input signal and a second input signal in accordance with a modifiable coefficient and to generate a second current by weighting and combining a first inverted signal and a second inverted signal in accordance with the coefficient, the first inverted signal being an inverted signal of the first input signal, the second inverted signal being an inverted signal of the second input signal; and a decision circuit configured to decide on an output signal by comparing the first current with the second current.

Abstract: An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together.

Abstract: An electronic circuit includes: a weighting circuit configured to generate a first current by weighting and combining a first input signal and a second input signal in accordance with a modifiable coefficient and to generate a second current by weighting and combining a first inverted signal and a second inverted signal in accordance with the coefficient, the first inverted signal being an inverted signal of the first input signal, the second inverted signal being an inverted signal of the second input signal; and a decision circuit configured to decide on an output signal by comparing the first current with the second current.

Abstract: An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.

Abstract: An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.

Abstract: A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error.

Abstract: A semiconductor integrated circuit includes first to N-th comparators to compare an input voltage with a threshold value; and a control circuit to perform first and second operations, set a threshold value of the first comparator as a first threshold value, and set a threshold value of an M-th comparator as a second threshold value, wherein the first operation includes an operation where a value obtained by multiplying a value obtained by subtracting the threshold value of the M-th comparator from a threshold value of an (M+1)th comparator by a real number is added to the threshold value of the M-th comparator, and wherein the second operation includes an operation where a value obtained by multiplying a value obtained by subtracting the threshold value of the M-th comparator from a threshold value of an (M?1)th comparator by a real number is added to the threshold value of the M-th comparator.

Abstract: A comparison circuit includes: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.

Abstract: A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error.

Abstract: A comparison circuit includes: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.

Abstract: A semiconductor integrated circuit includes first to N-th comparators to compare an input voltage with a threshold value; and a control circuit to perform first and second operations, set a threshold value of the first comparator as a first threshold value, and set a threshold value of an M-th comparator as a second threshold value, wherein the first operation includes an operation where a value obtained by multiplying a value obtained by subtracting the threshold value of the M-th comparator from a threshold value of an (M+1)th comparator by a real number is added to the threshold value of the M-th comparator, and wherein the second operation includes an operation where a value obtained by multiplying a value obtained by subtracting the threshold value of the M-th comparator from a threshold value of an (M?1)th comparator by a real number is added to the threshold value of the M-th comparator.

Abstract: A digital analog converter has an input terminal receiving a digital input signal, a lower-side capacitor group coupled to a lower-side common terminal in parallel, an upper-side capacitor group coupled, in parallel, to an upper-side common terminal at which an analog output signal is generated, a coupling capacitor provided between the lower-side common terminal and the upper-side common terminal, a switch group coupled to the upper-side capacitor group and the lower-side capacitor group and controlled as a conduction state and a non-conduction state in accordance with the digital input signal, and an adjusting capacitor coupled to the lower-side common terminal and having a variable capacitance value.

Abstract: A semiconductor device includes a first switching device including a first electrode coupled with a first node, a second electrode coupled with a second node, and a first control electrode controlling connection between the first and second electrodes; a second switching device including a third electrode coupled with the second node, a fourth electrode coupled with the second node, and a second control electrode controlling the connection between the third electrode and the fourth electrode; and a first control circuit controlling a substrate voltage of the second switching device.

Abstract: An analog signal processing device including a voltage selector selecting a given comparison reference voltage from plural comparison reference voltages, an arithmetic unit arithmetically processing the given comparison reference voltage and an analog input signal, a comparator which has at least one or more judgment points for the plural comparison reference voltages and to which an output of the arithmetic unit is inputted, and a coupling controller controlling connections between the arithmetic unit and the comparator, wherein the arithmetic unit comprises correctable first signal processors, and the number of the first signal processors is more than is necessary for the plural comparison reference voltages by M or larger, and when a set of N of first signal processors are in a correction operation, the coupling controller connects first signal processors which are not in the correction operation in the arithmetic unit to the comparator.

Abstract: A semiconductor device is described which includes a first comparator judging the level of an input signal based on a first judgment value, a second comparator judging the level of the input signal based on a second judgment value, and a calibrator outputting a control signal for starting the calibration of the second judgment value in the case that the calibration of the first judgment value is ended.

Abstract: A comparison circuit comprising: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.