Abstract: A process for fabricating an electrostatic chuck (20) comprising the steps of (c) forming a base (80) having an upper surface with cooling grooves (85) therein, the grooves sized and distributed for holding a coolant therein for cooling the base; and (d) pressure conforming an electrical insulator layer (45) to the grooves on the base by the steps of (i) placing the base into a pressure forming apparatus (25) and applying an electrical insulator layer over the grooves in the base; and (ii) applying a sufficiently high pressure onto the insulator layer to pressure conform the insulator layer to the grooves to form a substantially continuous layer of electrical insulator conformal to the grooves on the base.

Abstract: An electrostatic chuck (20) for holding a substrate (75) comprises (i) a base (80) having an upper surface (95) with grooves (85) therein, the grooves (85) sized and distributed for holding coolant for cooling a substrate (75), and (ii) a substantially continuous insulator film (45) conformal to the grooves (85) on upper surface (95) of the base (80). The base (80) can be electrically conductive and capable of serving as the electrode (50) of the chuck (20), or the electrode (50) can be embedded in the insulator film (45). The insulator film (45) has a dielectric breakdown strength sufficiently high that when a substrate (75) placed on the chuck (20) and electrically biased with respect to the electrode (50), electrostatic charge accumulates in the substrate (75) and in the electrode (50) forming an electrostatic force that attracts and holds the substrate (75) to the chuck (20).

Abstract: An apparatus for polishing semiconductor wafers and other workpieces that includes polishing pads mounted on respective platens at multiple polishing stations. Multiple wafer heads, at least one greater in number than the number of polishing stations, can be loaded with individual wafers. The wafer heads are suspended from a carousel, which provides circumferential positioning of the heads relative to the polishing pads, and the wafer heads oscillate radially as supported by the carousel to sweep linearly across the respective pads in radial directions with respect to the rotatable carousel. Each polishing station includes a pad conditioner to recondition the polishing pad so that it retains a high polishing rate. Washing stations may be disposed between polishing stations and between the polishing stations and a transfer and washing station to wash the wafer as the carousel moves. A transfer and washing station is disposed similarly to the polishing pads.

Abstract: A process for removing deposits from within a space at least partially delimited by a surface which is subject to attack from a plasma includes the steps of placing on the surface a cover comprising a material which is inert to the plasma, and then removing the deposits.

Abstract: A semiconductor wafer processing system for processing wafers from a wafer storage cassette includes a wafer transfer chamber; a wafer storage elevator within the transfer chamber; one or more wafer processing chambers; and a wafer transfer apparatus for transferring a wafer between a standard storage cassette adjacent and outside the transfer chamber and the elevator, and between the elevator and the processing chamber. The storage chamber pressure varies between atmospheric when accepting wafers from outside, and a subatmospheric pressure when transferring wafers to or from a processing chamber. The transfer apparatus includes a robot arm; a thin flat wafer carrying blade at the leading end of the robot arm configured for engaging a wafer from the storage cassette or the elevator; and a wafer support tray configured for removable engagement with the blade and for engaging and positively positioning a wafer from the elevator, or a support pedestal within a processing chamber.

Abstract: A semiconductor wafer processing system for processing wafers from a wafer storage cassette includes a wafer transfer chamber; a wafer storage elevator within the transfer chamber; one or more wafer processing chambers; and a wafer transfer apparatus for transferring a wafer between a standard storage cassette adjacent and outside the transfer chamber and the elevator, and between the elevator and the processing chamber. The storage chamber pressure varies between atmospheric when accepting wafers from outside, and a subatmospheric pressure when transferring wafers to or from a processing chamber. The transfer apparatus includes a robot arm; a thin flat wafer carrying blade at the leading end of the robot arm configured for engaging a wafer from the storage cassette or the elevator; and a wafer support tray configured for removable engagement with the blade and for engaging and positively positioning a wafer from the elevator, or a support pedestal within a processing chamber.

Abstract: A plasma process apparatus capacitor operation significantly above 13.56 MHz can produce reduced self-bias voltage of the powered electrode to enable softer processes that do not damage thin layers that are increasingly becoming common in high speed and high density integrated circuits. A nonconventional match network is used to enable elimination of reflections at these higher frequencies. Automatic control of match network components enables the rf frequency to be adjusted to ignite the plasma and then to operate at a variable frequency selected to minimize process time without significant damage to the integrated circuit.

Abstract: A semiconductor wafer processing system for processing wafers from a wafer storage cassette includes a wafer transfer chamber; a wafer storage elevator within the transfer chamber; one or more wafer processing chambers; and a wafer transfer apparatus for transferring a wafer between a standard storage cassette adjacent and outside the transfer chamber and the elevator, and between the elevator and the processing chamber. The storage chamber pressure varies between atmospheric when accepting wafers from outside, and a subatmospheric pressure when transferring wafers to or from a processing chamber. The transfer apparatus includes a robot arm; a thin flat wafer carrying blade at the leading end of the robot arm configured for engaging a wafer from the storage cassette or the elevator; and a wafer support tray configured for removable engagement with the blade and for engaging and positively positioning a wafer from the elevator, or a support pedestal within a processing chamber.

Abstract: A semiconductor wafer processing system for processing wafers from a wafer storage cassette includes a wafer transfer chamber; a wafer storage elevator within the transfer chamber; one or more wafer processing chambers; and a wafer transfer apparatus for transferring a wafer between a standard storage cassette adjacent and outside the transfer chamber and the elevator, and between the elevator and the processing chamber. The environment of the storage chamber varies in pressure between atmospheric when accepting wafers from outside, and a subatmospheric pressure when transferring wafers to or from a processing chamber.

Abstract: A process and apparatus is described for depositing a layer of material over the entire frontside surface of a semiconductor wafer without leaving residues on the backside of said wafer. A semiconductor wafer is placed on the surface of a first wafer support without contacting the frontside surface of the wafer to thereby permit access by deposition materials to the entire frontside surface of the wafer, and then a layer of material is deposited on the entire frontside surface of the semiconductor wafer. To remove any deposits formed on the backside of the wafer during such a deposition, the coated wafer is then placed generally coaxially on the surface of a generally circular second wafer support which will permit access to the outermost portions of the backside of the wafer. In one embodiment the second wafer support is provided with an annular groove coaxially formed in the surface of the second wafer support which faces the backside of the wafer.

Abstract: An improved process is described for forming planar tungsten-filled contacts to a silicon substrate in contact openings through an insulating layer which provides for the formation of titanium silicide in and on the silicon surface at the bottom of the contact openings to provide low resistance silicide interconnections between the silicon substrate and the tungsten. A titanium nitride layer is formed over the titanium silicide and on the surfaces of the insulation layer, including the top surface of the insulation layer and the sidewall surfaces of the contact openings through the insulating layer. This titanium nitride layer provides a nucleation layer which permits a good bond to form from the tungsten through the titanium nitride and titanium silicide in the contact openings to the silicon substrate; and from the tungsten through the titanium nitride layer to the insulator material such as silicon dioxide (SO.sub.2), resulting in the formation of low resistance and low defect density contacts.

Abstract: In a method for in situ cleaning a shield bearing of excess target material deposited in a physical vapor deposition chamber, during a cleaning cycle, a vacuum is created in the physical vapor deposition chamber. A gas mixture which includes a reactive gas is introduced into the physical vapor deposition chamber. The reactive gas is activated by plasma discharge. During the cleaning, the gas mixture is continuously removed from the vapor deposition chamber along with reaction products.

Abstract: An integrated modular multiple chamber vacuum processing system is disclosed. The system includes a load lock, may include an external cassette elevator, and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load lock chamber. A robot is mounted within the load lock and utilizes a concentric shaft drive system connected to an end effector via a dual four-bar link mechanism for imparting selected R-.theta. movement to the blade to load and unload wafers at the external elevator, internal elevator and individual process chambers. The system is uniquely adapted for enabling various types of IC processing including etch, deposition, sputtering and rapid thermal annealing chambers, thereby providing the opportunity for multiple step, sequential processing using different processes.

Abstract: An improved process is described for forming planar tungsten-filled contacts to a silicon substrate in contact openings through an insulating layer which provides for the formation of titanium silicide in and on the silicon surface at the bottom of the contact openings to provide low resistance silicide interconnections between the silicon substrate and the tungsten. A titanium nitride layer is formed over the titanium silicide and on the surfaces of the insulation layer, including the top surface of the insulation layer and the sidewall surfaces of the contact openings through the insulating layer. This titanium nitride layer provides a nucleation layer which permits a good bond to form from the tungsten through the titanium nitride and titanium silicide in the contact openings to the silicon substrate; and from the tungsten through the titanium nitride layer to the insulator material such as silicon dioxide (SO.sub.2), resulting in the formation of low resistance and low defect density contacts.

Abstract: A magnetic field enhanced single wafer plasma etch reactor is disclosed. The features of the reactor include an electrically-controlled stepped magnetic field for providing high rate uniform etching at high pressures; temperature controlled reactor surfaces including heated anode surfaces (walls and gas manifold) and a cooled wafer supporting cathode; and a unitary wafer exchange mechanism comprising wafer lift pins which extend through the pedestal and a wafer clamp ring. The lift pins and clamp ring are moved vertically by a one-axis lift mechanism to accept the wafer from a cooperating external robot blade, clamp the wafer to the pedestal and return the wafer to the blade. The electrode cooling combines water cooling for the body of the electrode and a thermal conductivity-enhancing gas parallel-bowed interface between the wafer and electrode for keeping the wafer surface cooled despite the high power densities applied to the electrode.

Abstract: A processing system for workpieces such as semiconductor wafers is disclosed which incorporates multiple, isolated vacuum stages between the cassette load lock station and the main vacuum processing chambers. A vacuum gradient is applied between the cassette load lock and the main processing chambers to facilitate the use of a very high degree of vacuum in the processing chambers without lengthy pump down times. Separate robot chambers are associated with the vacuum processing chambers and the load lock(s). In addition, separate transport paths are provided between the two robot chambers to facilitate loading and unloading of workpieces. Pre-treatment and post-treatment chambers may be incorporated in the two transport paths.

Abstract: An integrated modular multiple chamber vacuum processing system is disclosed. The system includes a load lock, may include an external cassette elevator, and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load lock chamber. A robot is mounted within the load lock and utilizes a concentric shaft drive system connected to an end effector via a dual four-bar link mechanism for imparting selected R-.theta. movement to the blade to load and unload wafers at the external elevator, internal elevator and individual process chambers. The system is uniquely adapted for enabling various types of IC processing including etch, deposition, sputtering and rapid thermal annealing chambers, thereby providing the opportunity for multiple step, sequential processing using different processes.

Abstract: A magnetic field enhanced single wafer plasma etch reactor is disclosed. The features of the reactor include an electrically-controlled stepped magnetic field for providing high rate uniform etching at high pressures; temperature controlled reactor surfaces including heated anode surfaces (walls and gas manifold) and a cooled wafer supporting cathode; and a unitary wafer exchange mechanism comprising wafer lift pins which extend through the pedestal and a wafer clamp ring. The lift pins and clamp ring are moved vertically by a one-axis lift mechanism to accept the wafer from a cooperating external robot blade, clamp the wafer to the pedestal and return the wafer to the blade. The electrode cooling combines water cooling for the body of the electrode and a thermal conductivity-enhancing gas parallel-bowed interface between the wafer and electrode for keeping the wafer surface cooled despite the high power densities applied to the electrode.

Abstract: A plasma CVD reactor and associated process use magnetic field enhancement to provide high quality, very high deposition rate metal, dielectric and conformal semiconductor films. The reacter and process are designed for automated, high-throughout, in-line small dimension VLSI integrated circuit fabrication, and are applicable to multistep in-situ processing.

Abstract: A magnetically-enhanced, variable magnetic field, RIE mode plasma etch process for etching materials such as dielectrics and polycrystalline, is disclosed. The variable magnetic field permits optimization of selected characteristics such as etch rate, etch selectivity, ion bombardment and radiation damage, etch uniformity, and etch anisotropy.