Patents by Inventor Satheesh Chellappan
Satheesh Chellappan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11792446Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.Type: GrantFiled: November 6, 2020Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Satheesh Chellappan, Kishore Kasichainula, Frank Baehren
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Publication number: 20220317855Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to process touch data. An example apparatus includes machine learning accelerator circuitry to execute a machine learning algorithm on touch data from touch sensor circuitry; and determine, based on an output of the machine learning algorithm, whether a touch input corresponding to the touch data was intentional; transceiver circuitry to, after a determination that the touch input was intentional, provide touch coordinates to memory; and processor circuitry to, after the determination that the touch input was intentional: access the touch coordinates in the memory; and perform an action based on the touch coordinates.Type: ApplicationFiled: June 24, 2022Publication date: October 6, 2022Inventors: Zhenyu Zhu, Satheesh Chellappan, Antonio Cheng, Kar Leong Wong
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Patent number: 11402893Abstract: Described is an apparatus comprising a first interface, a second interface, a third interface, and an interconnection fabric. The first interface may transfer a first stream of data traffic. The second interface, which may be an enhanced Serial Peripheral Interface (eSPI) interface, may transfer a second stream of data traffic and a third stream of data traffic. The third interface may transfer a fourth stream of data traffic. The interconnection fabric may couple the first interface to the second interface and may couple the second interface to the third interface. The second interface may initiate a transfer of an outbound data stream from one of the second stream of data traffic or the third stream of data traffic based on an available-space credit indicator. The second interface may receive an inbound data stream based upon the outbound data stream.Type: GrantFiled: January 7, 2019Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Zhenyu Zhu, Satheesh Chellappan, Mikal Hunsaker, Karthi R. Vadivelu, Kar Leong Wong
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Publication number: 20220217099Abstract: Techniques are provided for on-chip communication. A system implementing the techniques according to an embodiment includes a first virtual physical (vPhy) circuit couplable to a host through a vPhy interface and a second vPhy circuit couplable to a device, on the same chip as the host, through another vPhy interface. The system further includes a vPhy-to-vPhy interface between the vPhy circuits which includes signal lines to transmit a first data toggle signal from the first vPhy circuit to the second vPhy circuit, and a second data toggle signal from the second vPhy circuit to the first vPhy circuit. The first vPhy circuit is configured to generate the first data toggle signal based on a signal received from the host for transmission to the device. The second vPhy circuit is configured to generate the second data toggle signal based on signal received from the device for transmission to the host.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Applicant: Intel CorporationInventors: Kar Leong Wong, Satheesh Chellappan
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Publication number: 20220179821Abstract: In one embodiment, a system includes a host system-on-chip (SoC) comprising vision processing circuitry and a camera connected to the host SoC through an Inter-Integrated Circuit (I3C) bus. The camera includes circuitry to generate image data and transmit an interrupt signal to the host SoC over the I3C bus indicating the image data is ready for transfer. The host SoC vision processing circuitry is to transmit a read message to the camera over the I3C bus based on the interrupt signal and receive a set of line payload packets including the image data over the I3C bus based on the read message.Type: ApplicationFiled: February 25, 2022Publication date: June 9, 2022Inventors: Satheesh Chellappan, Haran Thanigasalam
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Publication number: 20220164130Abstract: A system, article, and method of standards-based audio function processing has reduced memory usage by using an address mapping table.Type: ApplicationFiled: February 8, 2022Publication date: May 26, 2022Applicant: Intel CorporationInventors: Satheesh Chellappan, Tomasz Pielaszkiewicz, Devon Worrell
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Patent number: 11308791Abstract: The disclosure generally provides methods, systems and apparatus for functional safety systems. Specifically, the disclosure relates to validating functional safety warnings that may be communicated to an operator. Such warnings may include safety warning chimes.Type: GrantFiled: December 28, 2018Date of Patent: April 19, 2022Assignee: INTEL CORPORATIONInventors: Satheesh Chellappan, Srikanth Potluri
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Publication number: 20220113758Abstract: System and techniques for selectable clock sources are described herein. An electronic device includes an oscillator for a first clock signal and a tap on an input signal line to a resonator for the oscillator. The tap enables receipt of a second clock signal from an external oscillator. The electronic device includes mode selection circuitry to receives a signal from a tap to an existing input line to the electronic device. The mode selection circuitry uses this signal to select the oscillator output as the clock source or the tap on the input signal line as the clock source.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventors: Kishore Kasichainula, Satheesh Chellappan
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Publication number: 20210266610Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.Type: ApplicationFiled: November 6, 2020Publication date: August 26, 2021Inventors: Satheesh Chellappan, Kishore Kasichainula, Frank Baehren
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Patent number: 10834434Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.Type: GrantFiled: December 28, 2018Date of Patent: November 10, 2020Assignee: Intel CorporationInventors: Satheesh Chellappan, Kishore Kasichainula, Frank Baehren
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Patent number: 10788533Abstract: Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.Type: GrantFiled: August 29, 2018Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Kishore Kasichainula, Satheesh Chellappan, Lay Chen Ong, Harish G. Kamat
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Patent number: 10705142Abstract: Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.Type: GrantFiled: December 29, 2016Date of Patent: July 7, 2020Assignee: INTEL CORPORATIONInventors: Lakshminarayana Pappu, Suketu U. Bhatt, Satheesh Chellappan
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Patent number: 10606772Abstract: In one example a Universal Serial Bus (USB) controller comprises at least one memory register to store one or more enumeration parameters for a USB connection with the USB controller and logic, at least partially including hardware logic, to detect a USB connection with a remote device via the USB connection, retrieve one or more connection enumeration parameters for the USB connection from the at least one memory register on the USB host controller, and implement a connection enumeration process using the one or more connection enumeration parameters retrieved from the memory register on the USB controller. Other examples may be described.Type: GrantFiled: April 17, 2018Date of Patent: March 31, 2020Assignee: INTEL CORPORATIONInventors: Satheesh Chellappan, Kishore Kasichainula, Lay Cheng Ong, Chee Lim Poon, Harish G. Kamat
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Patent number: 10417170Abstract: Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information—e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.Type: GrantFiled: March 31, 2017Date of Patent: September 17, 2019Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Suketu Bhatt, Satheesh Chellappan
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Patent number: 10366017Abstract: An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.Type: GrantFiled: March 30, 2018Date of Patent: July 30, 2019Assignee: Intel CorporationInventors: Darren Abramson, David Hines, Alberto Martinez, Adeel Aslam, John Howard, Shanthanand R. Kutuva, Karthi R. Vadivelu, Kar Leong Wong, Satheesh Chellappan
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Publication number: 20190158890Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.Type: ApplicationFiled: December 28, 2018Publication date: May 23, 2019Inventors: Satheesh Chellappan, Kishore Kasichainula, Frank Baehren
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Publication number: 20190155371Abstract: Described is an apparatus comprising a first interface, a second interface, a third interface, and an interconnection fabric. The first interface may transfer a first stream of data traffic. The second interface, which may be an enhanced Serial Peripheral Interface (eSPI) interface, may transfer a second stream of data traffic and a third stream of data traffic. The third interface may transfer a fourth stream of data traffic. The interconnection fabric may couple the first interface to the second interface and may couple the second interface to the third interface. The second interface may initiate a transfer of an outbound data stream from one of the second stream of data traffic or the third stream of data traffic based on an available-space credit indicator. The second interface may receive an inbound data stream based upon the outbound data stream.Type: ApplicationFiled: January 7, 2019Publication date: May 23, 2019Inventors: Kevin Zhenyu Zhu, Satheesh Chellappan, Mikal Hunsaker, Karthi R. Vadivelu, Kar Leong Wong
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Publication number: 20190139399Abstract: The disclosure generally provides methods, systems and apparatus for functional safety systems. Specifically, the disclosure relates to validating functional safety warnings that may be communicated to an operator. Such warnings may include safety warning chimes.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Applicant: Intel CorporationInventors: Satheesh Chellappan, Srikanth Potluri
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Publication number: 20190101592Abstract: Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.Type: ApplicationFiled: August 29, 2018Publication date: April 4, 2019Applicant: Intel CorporationInventors: Kishore Kasichainula, Satheesh Chellappan, Lay Chen Ong, Harish G. Kamat
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Publication number: 20190042483Abstract: An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.Type: ApplicationFiled: March 30, 2018Publication date: February 7, 2019Inventors: Darren Abramson, David Hines, Alberto Martinez, Adeel Aslam, John Howard, Shanthanand R. Kutuva, Karthi R. Vadivelu, Kar Leong Wong, Satheesh Chellappan