Patents by Inventor Satoshi Aida
Satoshi Aida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050258503Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.Type: ApplicationFiled: July 22, 2005Publication date: November 24, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Kazuya Nakayama, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
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Publication number: 20050250322Abstract: There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode region connected with at least the semiconductor region and a part of the pillar region, a control electrode and an electrode pad connected with the control electrode. The pillar region including a first region of a first conductivity type and a second region of a second conductivity type is not formed under the electrode pad. Also, a method for manufacturing a MISFET is provided.Type: ApplicationFiled: March 31, 2005Publication date: November 10, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Satoshi Yanagisawa, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20050194638Abstract: A semiconductor device comprises a semiconductor element and a conductive member. The semiconductor element has a semiconductor substrate having first and second major surfaces; a semiconductor layer formed on the first major surface of the semiconductor substrate; a plurality of trenches formed on the semiconductor layer, the trenches being parallel to each other and extending to a first direction; filling material filling the trenches; a first electrode pad provided on the semiconductor layer and connected electrically to a first major electrode; a second major electrode provided on the second major surface; and a gate electrode pad provided on the semiconductor layer and connected to a gate electrode which controls conduction between the first major electrode and the second major electrode. The conductive member is connected to at least one of the first electrode pad and the gate electrode pad via a first contact area.Type: ApplicationFiled: October 29, 2004Publication date: September 8, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeo Kouzuki, Satoshi Aida, Satoshi Yanagisawa, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 6930352Abstract: An insulated gate semiconductor device includes a control electrode having a trench type structure formed on the surface of a first semiconductor layer of a first conductivity type via a gate insulation film and disposed in a lattice shape, the control electrode having a plurality of first control electrode sections and a plurality of second control electrode sections which intersect with the plurality of first control electrode sections, respectively, and a plurality of fifth semiconductor layers of a second conductivity type which are provided on an interface of the first semiconductor layer in contact with the plurality of second control electrode sections, and connected to at least one of a plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layers having impurity concentration lower than that of the plurality of second semiconductor layers.Type: GrantFiled: June 18, 2003Date of Patent: August 16, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura, Satoshi Aida
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Patent number: 6849880Abstract: A power semiconductor device includes second layers of a second conductivity type disposed in a first layer of a first conductivity type. The second layers extend in a depth direction and are arrayed at intervals. Third layers of the second conductivity type are disposed respectively in contact with the second layers. Fourth layers of the first conductivity type are respectively formed in surfaces of the third layers. A gate electrode faces, through a first insulating film, a channel region, which is each of portions of the third layers interposed between the fourth layers and the first layer. An additional electrode is disposed on each of the second layers through a second insulating film, and faces, through each of the second layers, the first main electrode. The additional electrode is electrically connected to the gate electrode.Type: GrantFiled: March 9, 2004Date of Patent: February 1, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura, Satoshi Aida
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Patent number: 6849900Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first coType: GrantFiled: June 27, 2003Date of Patent: February 1, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka, Wataru Saito
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Publication number: 20040251516Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of a first conductivity type formed on a first main surface of the semiconductor substrate, a surface of the drift layer having a first area and a second area which is positioned on an outer periphery of the first area; a cell portion which is formed in the first area of the drift layer and includes a first base layer of a second conductivity type selectively formed in a surface layer of the first area, a source layer of a first conductivity type selectively formed in a surface layer of the first base layer, a first metallic compound which is formed on the surface layer of the first base layer and a surface layer of the source layer in common, and a control electrode which is formed in the first base layer and the source layer via a first insulating film and has a second metallic compound formed on a top surface thereof; a terminating portion which is formed in the second area of the drift layer, alleviatesType: ApplicationFiled: October 8, 2003Publication date: December 16, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20040206989Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first coType: ApplicationFiled: June 27, 2003Publication date: October 21, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka, Wataru Saito
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Publication number: 20040195618Abstract: An insulated gate semiconductor device includes a control electrode having a trench type structure formed on the surface of a first semiconductor layer of a first conductivity type via a gate insulation film and disposed in a lattice shape, the control electrode having a plurality of first control electrode sections and a plurality of second control electrode sections which intersect with the plurality of first control electrode sections, respectively, and a plurality of fifth semiconductor layers of a second conductivity type which are provided on an interface of the first semiconductor layer in contact with the plurality of second control electrode sections, and connected to at least one of a plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layers having impurity concentration lower than that of the plurality of second semiconductor layers.Type: ApplicationFiled: June 18, 2003Publication date: October 7, 2004Inventors: Wataru Saito, Ichiro Omura, Satoshi Aida
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Publication number: 20040140521Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.Type: ApplicationFiled: October 29, 2003Publication date: July 22, 2004Inventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiro Osawa, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
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Patent number: 6740931Abstract: A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.Type: GrantFiled: April 17, 2003Date of Patent: May 25, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Kouzuki, Hideki Okumura, Hitoshi Kobayashi, Satoshi Aida, Masaru Izumisawa, Akihiko Osawa
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Patent number: 6700156Abstract: An insulated gate semiconductor device includes a first semiconductor layer of a first conductivity type. A plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the first semiconductor layer. At least one third semiconductor layer of the first conductivity type is formed in a surface area of each of the second semiconductor layers. A fourth semiconductor layer is formed on a bottom of the first semiconductor layer. At least one fifth semiconductor layer of the second conductivity type is provided in the first semiconductor layer and connected to at least one of the plurality of second semiconductor layers. The fifth semiconductor layer has impurity concentration that is lower than that of the second semiconductor layers.Type: GrantFiled: December 18, 2002Date of Patent: March 2, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saitoh, Ichiro Omura, Satoshi Aida
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Patent number: 6693338Abstract: A semiconductor device includes a drain layer, first and second drift layers, a RESURF layer, a drain electrode, a base layer, a source layer, a source electrode, and a gate electrode. The first drift layer is formed on the drain layer. The second drift layers and RESURF layers are formed on the first drift layer and periodically arranged in a direction perpendicular to the direction of depth. The RESURF layer forms a depletion layer in the second drift layer by a p-n junction including the second drift layer and RESURF layer. The impurity concentration in the first drift layer is different from that in the second drift layer. The drain electrode is electrically connected to the drain layer.Type: GrantFiled: June 7, 2002Date of Patent: February 17, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saitoh, Ichiro Omura, Masakazu Yamaguchi, Satoshi Aida, Syotaro Ono
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Publication number: 20040016962Abstract: There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.Type: ApplicationFiled: April 24, 2003Publication date: January 29, 2004Inventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiko Osawa, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
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Publication number: 20040012038Abstract: A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.Type: ApplicationFiled: April 17, 2003Publication date: January 22, 2004Inventors: Shigeo Kouzuki, Hideki Okumura, Hitoshi Kobayashi, Satoshi Aida, Masaru Izumisawa, Akihiko Osawa
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Publication number: 20040007766Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.Type: ApplicationFiled: May 28, 2003Publication date: January 15, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuya Nakayama, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
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Publication number: 20030209741Abstract: An insulated gate semiconductor device includes a plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of a first semiconductor layer of a first conductivity type. At least one third semiconductor layer of the first conductivity type is formed in a surface area of each of the second semiconductor layers. A fourth semiconductor layer is formed on the bottom of the first semiconductor layer. At least one fifth semiconductor layer of the second conductivity type is provided in the first semiconductor layer and connected to at least one of the plurality of second semiconductor layers. The fifth semiconductor layer has impurity concentration that is lower than that of the second semiconductor layers.Type: ApplicationFiled: June 28, 2002Publication date: November 13, 2003Inventors: Wataru Saitoh, Ichiro Omura, Satoshi Aida
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Publication number: 20030201456Abstract: An insulated gate semiconductor device includes a first semiconductor layer of a first conductivity type. A plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the first semiconductor layer. At least one third semiconductor layer of the first conductivity type is formed in a surface area of each of the second semiconductor layers. A fourth semiconductor layer is formed on a bottom of the first semiconductor layer. At least one fifth semiconductor layer of the second conductivity type is provided in the first semiconductor layer and connected to at least one of the plurality of second semiconductor layers. The fifth semiconductor layer has impurity concentration that is lower than that of the second semiconductor layers.Type: ApplicationFiled: December 18, 2002Publication date: October 30, 2003Inventors: Wataru Saitoh, Ichiro Omura, Satoshi Aida
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Publication number: 20030149380Abstract: An ultrasound treatment apparatus includes an ultrasound source for generating treatment ultrasound which is focused, a driving circuit for driving the ultrasound source to generate treatment ultrasound from the ultrasound source, and a controller for controlling to make the driving circuit drive the ultrasound source under an irradiation condition in which an optimization index obtained by the product of the focus intensity (W/cm2), the irradiation period (sec), and the frequency (MHz) all of the treatment ultrasound falls within an appropriate range from 6,000 (inclusive) to 40,000 (inclusive).Type: ApplicationFiled: February 11, 2003Publication date: August 7, 2003Inventors: Katsuhiko Fujimoto, Satoshi Aida, Yoichi Takada, Hideki Kosaku, Yoichi Hazama
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Patent number: 6540700Abstract: An ultrasound treatment apparatus includes an ultrasound source for generating treatment ultrasound which is focused, a driving circuit for driving the ultrasound source to generate treatment ultrasound from the ultrasound source, and a controller for controlling to make the driving circuit drive the ultrasound source under an irradiation condition in which an optimization index obtained by the product of the focus intensity (W/cm2), the irradiation period (sec), and the frequency (MHZ) all of the treatment ultrasound falls within an appropriate range from 6,000 (inclusive) to 40,000 (inclusive).Type: GrantFiled: October 25, 1999Date of Patent: April 1, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Fujimoto, Satoshi Aida, Yoichi Takada, Hideki Kosaku, Yoichi Hazama