Abstract: A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

Abstract: In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor, a voltage supplying circuit configured to supply a voltage to one of the terminals of the first driver transistor and one of the terminals of the second driver transistor, the voltage which is one of more than a GND voltage and less than a GND voltage.

Abstract: A semiconductor device has a plurality of fins formed on a semiconductor substrate to be separated from each other, a first contact region which connects commonly one end side of the plurality of fins, a second contact region which connects commonly the other end side of the plurality of fins, a gate electrode arranged to be opposed to at least both side surfaces of the plurality of fins by sandwiching a gate insulating film therebetween, a source electrode including the first contact region and the plurality of fins on a side closer to the first contact region than the gate electrode, and a drain electrode including the second contact region and the plurality of fins on a side closer to the second contact than the gate electrode. The ratio Rd/Rs of a resistance Rd of each fin in the drain region to a resistance Rs of each fin in the source region is larger than 1.

Abstract: A semiconductor device of an embodiment includes a substrate and a plurality of fins formed on the substrate. The plurality of fins is arranged so that a first distance and a second distance narrower than the first distance are repeated. In addition, the plurality of fins include a semiconductor region in which an impurity concentration of lower portions of side surfaces facing each other in sides forming the first distance is higher than an impurity concentration of lower portions of side surfaces facing each other in sides forming the second distance.

Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

Abstract: A semiconductor device includes a circuit comprising a first transistor in a first Fin; a power supply circuit in a second Fin, the power supply circuit comprising a second transistor connected between the circuit and a power supply line; and a substrate contact electrically connected to the semiconductor substrate and configured to apply a substrate voltage to a substrate, wherein a width of the first Fin in a cross-section of the first Fin perpendicular to a channel length direction of the first transistor is equal to or smaller than a twofold of a largest depletion layer width of a depletion layer formed in a channel part of the first transistor, and a width of the second Fin in a cross-section of the second Fin perpendicular to a channel length direction of the second transistor is larger than a twofold of a largest depletion layer width of a depletion layer in a channel of the second transistor.

Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a mask material on a semiconductor substrate comprising first and second regions; forming a pattern of a core on the mask material in the first region; forming a sidewall spacer mask on a side surfaces of the core pattern and subsequently removing the core pattern; transferring a pattern of the sidewall spacer mask to the mask material in the first region after removing the core; and thereafter, carrying out trimming of the pattern of the sidewall spacer mask which is transferred to the mask material in the first region, and formation of a predetermined pattern on the mask material in the second region, simultaneously.

Abstract: In one aspect of the present invention, a semiconductor device may include a Si substrate, a gate electrode provided on the semiconductor via a gate dielectric layer, a first epitaxially grown layer provided on the Si substrate, a channel region provided in the Si substrate below the gate electrode, a source/drain region provided in the first epitaxially grown layer sandwiching the channel region, and having a first conductivity type impurity, a second epitaxially grown layer provided between the channel region and the first epitaxially grown layer, and provided below the gate electrode, and having a second conductivity type impurity opposite to the first conductivity type.

Abstract: A first electrode is formed on a semiconductor substrate. A second electrode is formed separately at a predetermined interval from the first electrode, and has at least one opening. An actuator layer is connected to the second electrode, and drives the second electrode.

Abstract: In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor, a voltage supplying circuit configured to supply a voltage to one of the terminals of the first driver transistor and one of the terminals of the second driver transistor, the voltage which is one of more than a GND voltage and less than a GND voltage.

Abstract: A semiconductor device includes N fins made of semiconductor regions aligned in parallel with each other in the top view plain, a gate electrode formed on both side surfaces of each of the N fins to cross the fins, source/drain layers formed in each of the N fins by sandwiching the gate electrode, a first wiring connected to one of the source/drain layers via a first contact formed in each of M fins, and a second wiring connected to the other one of the source/drain layers via a second contact formed in each of K fins.

Abstract: In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor, a voltage supplying circuit configured to supply a voltage to one of the terminals of the first driver transistor and one of the terminals of the second driver transistor, the voltage which is one of more than a GND voltage and less than a GND voltage.

Abstract: A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

Abstract: A semiconductor device according to an embodiment of the invention includes: a semiconductor substrate; device regions formed on the semiconductor substrate, the device regions having a length direction in a predetermined direction; a plurality of transistors having gate electrodes, respectively, the gate electrodes extending in a direction approximately perpendicular to the predetermined direction, the plurality of transistors having a source/drain region and a channel region having a channel direction approximately parallel to the predetermined direction in the device region; a plurality of SRAM cells disposed in an array, each of the plurality of SRAM cells including the plurality of transistors; and a dummy region made of the substantially same material as that of the device regions, the dummy region being formed between the outermost device regions of the SRAM cells adjacent to each other in the direction approximately perpendicular to the predetermined direction, the dummy region having a length directi

Abstract: A semiconductor memory having a plurality of static random access memory cells, word lines, first and second bit lines orthogonal to the word lines, and threshold voltage control lines parallel to the word lines and each of the static random access memory cell includes the first and the second driver transistors, the first and the second load transistors, and the first and the second transfer transistors configured by Fin field effect transistors, and at least one of the Fin field effect transistors is configured by a separated-gate type double-gate field effect transistor comprising a first gate electrode and a second gate electrode and controlling a voltage for the first gate electrode to form a channel, and controlling a voltage for the second gate electrode to decrease a threshold voltage at the time of writing data.

Abstract: A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer.

Abstract: A semiconductor device has a plurality of fins formed on a semiconductor substrate to be separated from each other, a first contact region which connects commonly one end side of the plurality of fins, a second contact region which connects commonly the other end side of the plurality of fins, a gate electrode arranged to be opposed to at least both side surfaces of the plurality of fins by sandwiching a gate insulating film therebetween, a source electrode including the first contact region and the plurality of fins on a side closer to the first contact region than the gate electrode, and a drain electrode including the second contact region and the plurality of fins on a side closer to the second contact than the gate electrode. The ratio Rd/Rs of a resistance Rd of each fin in the drain region to a resistance Rs of each fin in the source region is larger than 1.

Abstract: In one aspect of the present invention, a semiconductor device, may include a fin formed of a semiconductor layer protruding straight from a semiconductor substrate, the fin includes straight portion which extends in a direction in a plan view and a bent portion which extends in a direction different from the direction, the straight portion and the bent portion being continuously connected, a gate insulating film provided on side surfaces of the straight portion of the fin, a gate electrode provided on the gate insulating film, source and drain regions provided in the straight portion of the fin so as to sandwich the gate electrode, a contact region provided on the straight portion of the fin and the bent portion of the fin, the contact region being electrically connected to one of the source and drain regions, and a contact member provided on the contact region of the fin so as to in contact with both of the straight portion and the bent portion of the contact region.

Abstract: A semiconductor device according to an aspect of the invention comprises an n-type FinFET which is provided on a semiconductor substrate and which includes a first fin, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at both end of the first fin, a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at both end of the second fin, wherein the n- and the p-type FinFET constitute an inverter circuit, and the fin width of the contact region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET.