Abstract: A semiconductor device is mounted on a package substrate which has a power supply line and a signal line formed of a normal or predetermined resistance material layer on a dielectric layer. A resistance material layer has a high resistance as compared with the normal resistance material layer and is additionally provided on the surface of the normal resistance material layer of the peripheral face of the signal line closest to the power supply line.

Abstract: A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

Abstract: A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad.

Abstract: Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.

Abstract: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.

Abstract: A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

Abstract: To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power supply wiring layer 6 electrically connected to a semiconductor chip and a ground wiring layer 4, so composed that a dielectric loss generated in the second dielectric layer 5 acts as a low pass filter of the power supply wiring layer 6, and having a first dielectric layer 3 made of dielectric material whose dielectric loss is less than the dielectric loss tan 6 of the second dielectric layer 5 and interposed between a signal wiring layer 2 electrically connected to the semiconductor chip and the ground wiring layer 4.

Abstract: A semiconductor apparatus comprises a resistor formed in a driver to connect a driving device to a transmission line connecting the driver to a receiver. The resistor has resistance considerably larger than on-state resistance of the driving device on condition that the resistor matches output impedance of the driver with impedance of the transmission line. The transmission line has length decided so that a reflected wave from a receiver-side end of the transmission line reaches the driver while a driving signal supplied to the driver has a logical high or low level.

Abstract: A semiconductor device has a semiconductor chip which is usable as any one of 4-bit, 8-bit, and 16-bit structure devices, and a package for packaging the semiconductor chip. The semiconductor chip has first and second DQ pad groups of DQ system pads for said 16-bit structure device. The first DQ pad group is arranged in a first area at a vicinity of a middle part of a surface of the semiconductor chip while the second DQ pad group is arranged in a second area at an outer side of the first area on the surface. An additional pad necessary as one of DQ system pads for the 8-bit structure device except for pads included in the second DQ pad group is formed in the second area.

Abstract: A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.

Abstract: Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.

Abstract: A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.

Abstract: System, method and program for inductance analysis for reducing time for analysis, to cope with increase in the system size, to achieve high accuracy in the analysis. Information on a power supply plane, in a state in which a beginning point of non-coupled current of return current accompanying a signal current is placed in the vicinity of a signal through-hole on the power supply plane, based on position information of said signal through-hole, is received. Potential distribution in the power supply plane is determined and output. The non-coupled inductance from the signal through-hole to the power supply through-hole in the power supply plane is evaluated. In the potential analysis, non-coupled inductance L from the signal through-hole to the power supply through-hole is represented by resistance R.

Abstract: A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.

Abstract: A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

Abstract: In a multilayer interconnection layer of a mother board and a memory module, a position relationship between a bus interconnection layer and a conductive layer of a power supply layer or a ground layer opposite to the bus interconnection layer is substantially held in not only the mother board but also the memory module and a relationship of multilayer interconnections is unified. As a result, it is possible to reduce disturbance of a return current of a high frequency signal given to the bus interconnection layer, to prevent degradation of quality of a signal waveform caused by the disturbance of the return current, and to prevent unnecessary electromagnetic waves from radiating caused by the disturbance of the return current.

Abstract: To increase data transfer rate of a memory system in which a plurality of memory modules are stacked using mezzanine connectors, stacked blind vias and buried vias for connecting only specific layers are used as vias in a multilayer circuit board serving as a memory module board, and at least some of pads for mounting devices have a pad-on-via structure. Thus, the vias have no redundant portions which are not required for signal transmission and the length of surface-layer wiring can be remarkably reduced.

Abstract: A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.

Abstract: In a multilayer interconnection layer of a mother board and a memory module, a position relationship between a bus interconnection layer and a conductive layer of a power supply layer or a ground layer opposite to the bus interconnection layer is substantially held in not only the mother board but also the memory module and a relationship of multilayer interconnections is unified. As a result, it is possible to reduce disturbance of a return current of a high frequency signal given to the bus interconnection layer, to prevent degradation of quality of a signal waveform caused by the disturbance of the return current, and to prevent unnecessary electromagnetic waves from radiating caused by the disturbance of the return current.

Abstract: A semiconductor apparatus comprises a resistor formed in a driver to connect a driving device to a transmission line connecting the driver to a receiver. The resistor has resistance considerably larger than on-state resistance of the driving device on condition that the resistor matches output impedance of the driver with impedance of the transmission line. The transmission line has length decided so that a reflected wave from a receiver-side end of the transmission line reaches the driver while a driving signal supplied to the driver has a logical high or low level.