Abstract: The present semiconductor memory device is provided with plurality of memory cell array blocks, a plurality of redundant memory cell lines, a replacement address program circuit outputting active level redundant selection signals on predetermined occasions, a replacement judging circuit outputting active level replacement judging signals on predetermined occasions, a redundancy selection signal encoder encoding redundancy selection signals inputted by the replacement address program and outputting them as redundancy selection encode signals, and a replacement control circuit decoding a plurality of redundancy selection encode signals inputted by the redundancy selection signal encoder when the replacement judging signals are at active level, selecting from among them redundancy memory cell lines corresponding to active level redundancy selection signals, and driving the selected redundancy memory cell lines by the redundancy line decoder.

Abstract: A semiconductor memory device is provided which is capable of realizing a redundancy memory cell test to be performed before a defective memory cell is replaced by a redundancy memory cell with a small size circuit provided therein. The semiconductor memory device includes a redundancy address program circuit programmed such that a redundancy memory cell is selected when an address for selecting a defective memory cell, for generating a redundancy selection signal, and a circuit for receiving a redundancy circuit test mode signal which is made active when the redundancy memory cell is tested before the redundancy address program circuit is programmed to generate a portion of the input address as a portion of the address of the redundancy memory cell when the redundancy circuit test mode signal is active and generate the redundancy selection signal as a portion of the address of the redundancy memory cell when the redundancy circuit test mode signal is inactive.

Abstract: A semiconductor memory device comprises: an internal clock signal generating circuit that generates first and second internal clock signals for the internal timing control in response to an external clock; a first latch circuit that includes a first switching means to operate synchronously with the first internal clock signal and latches a plurality of command control signals for the internal operation control and outputs a plurality of latch command signals; a command decoding circuit that decodes the plurality of latch command signals and outputs a plurality of command decode signals; and a latch circuit that includes a second switching means to operate synchronously with the second internal clock signal, latches the plurality of command decode signals and outputs a plurality of predetermined mode signals.

Abstract: For preventing skews between connecting timing of local I/O lines to global I/O lines and that to bit lines and reducing chip size as well, a semiconductor memory device, having a plurality of banks (10a and 10b) each comprising a plurality of sub-arrays (20) arranged in matrix, global I/O-line pairs (40) extending in a y-direction traversing the banks (10a and 10b) and each shared by two columns of the sub-arrays (20), local I/O-line pairs (30) extending in a x-direction and each traversing sub-arrays (20) of each row of the two columns, and column-selection lines (33) extending in the y-direction traversing the sub-arrays of columns of each of the banks (10a and 10b) for selecting bit-line pairs (34) to be connected to the local I/O-line pairs, comprises I/O switch lines (60), whereof each is extending along with each of the global I/O-line pairs in each of the banks (10a and 10b), for transmitting a column-activating signal for connecting the global I/O-line pairs (40) to the local I/O-line pairs (30) of a

Abstract: In a semiconductor memory device including a plurality of memory cells connected between sub word lines and bit lines, a plurality of sub word line driver columns for driving the sub word lines, and a plurality of sense amplifier columns for sensing voltages at the bit lines, a plurality of sense amplifier control circuits are provided at cross areas between the sub word line driver columns and the sense amplifier columns. A first sense amplifier control circuit is constructed by a CMOS circuit forming an interface between global input/output lines and local input/output lines. A second sense amplifier control circuit is constructed by an N-channel MOS circuit forming a pull down circuit for pulling down NMOS sources of flip-flops of the sense amplifier columns and a first pull up circuit for pulling up PMOS sources of the flip-flops of said sense amplifier columns.

Abstract: Shortening setup and hold times by equalizing the signal propagation delay time between input buffer circuits and D-F/F circuit to which are supplied command control signals CSB, RASB, CASB, and WEB supplied from a plurality of external terminals, and synchronizing these command control signals with the internal clock signal ICLK, batch loading these into D-F/F circuit and holding this signal, sending it from decode circuits after decoding, and latching it with latch circuits by means of internal clock delay signal ICLKD generated and delayed by internal clock signal ICLK thus being capable of shortening setup time and hold time in a synchronous DRAM.

Abstract: In a semiconductor memory device including a plurality of memory cell blocks and a plurality of redundant memory cell arrays each corrsponding to one of the memory cell blocks, a first selecting circuit selects memory cells from the memory cell blocks. Also, a redundant selection signal generating circuit generates redundant selection signals for the redundant memory cell arrays, and a redundant selection signal encoder encodes the redundant selection signals into redundant encode signals. A second selecting circuit decodes the redundant encode signals to select redundant memory cells from the redundant memory cell arrays. Further, when one of the redundant selection signals is generated, a deactivating circuit deactivates the first selecting circuit.

Abstract: A semiconductor memory device capable of restricting an increase of a gate capacitance of a substitution address program circuit connected to an address bus and reducing charge/discharge current of the substitution address program circuit to reduce current consumption of a chip and to restrict an increase of time from a time instance when an address signal is input to a time instance when a redundancy selection signal is output is provided. Addresses containing defects are programmed by fuses 2 and a node PRE has a potential swung between a first potential which is lower than a power source potential and higher than a reference potential VREF which is set to an intermediate potential between the power source potential and a ground potential and a second potential lower than the reference potential and higher than the ground potential.

Abstract: A redundancy decoder circuit includes an output line U which takes an active level when an access address supplied thereto is coincident with a redundant address programmed therein. This circuit further includes a fuse F which is blown to deactivate the decoder or not blown to activate the decoder, a latch circuit latching a level responsive to a blown or not-blown state of the fuse, and a transistor controlled by the latch circuit to forcibly hold the output line at an inactive level when the fuse is blown.