Patents by Inventor Scott Bell

Scott Bell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7521304
    Abstract: A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: April 21, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Huang, Scott A. Bell, Srikanteswara Dakshina-Murthy, Philip A. Fisher, Richard C. Nguyen, Cyrus E. Tabery, Lu You
  • Patent number: 7498222
    Abstract: A high K layer, such as aluminum oxide or hafnium oxide, may be formed with a deposition process that uses an ion implantation to damage portions of the high K material that are to be later etched. More particularly, in one implementation, a semiconductor device is manufactured by forming a first dielectric over a substrate, forming a charge storage element over the first dielectric, forming a second dielectric above the charge storage element, implantation ions into select portions of the second dielectric, and etching the ion implanted select portions of the second dielectric.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: March 3, 2009
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: John C. Foster, Scott Bell, Allison Holbrook, Simon S. Chan, Phillip Jones
  • Patent number: 7465644
    Abstract: A structure for electrically isolating semiconductor devices includes a semiconducting layer and a layer of aluminum oxide formed in a pattern over the semiconducting layer, where the pattern exposes a portion of the semiconducting layer. The structure further includes an electrical isolation region formed in the exposed portion of the semiconducting layer, where the isolation region does not substantially encroach a region beneath the layer of aluminum oxide.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: December 16, 2008
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Simon S. Chan, Weidong Qian, Scott Bell, Phillip Jones, Allison Holbrook
  • Patent number: 7457952
    Abstract: An authentication apparatus includes a reading or recording medium equipped with an authentication tag, and a reading and recording drive that includes a transmitter and a coupler chip, wherein the authentication tag and the transmitter are capable of communicating with each other when the reading medium or the recording medium is coupled to the reading and recording drive. An authentication method includes providing a reading medium or a recording medium with an authentication tag, providing a reading and/or recording drive with a transmitter and a communication interface wherein the authentication tag and the transmitter are capable of communicating with each other when the reading medium or recording medium is coupled to the reading and/or recording drive, and authenticating the reading medium or recording medium via a communication between the authentication tag and the transmitter.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: November 25, 2008
    Assignee: Xerox Corporation
    Inventors: Alberto Rogriguez, Heiko Rommelmann, Scott Bell, Will Phipps, Ron Boucher
  • Publication number: 20080254607
    Abstract: Systems and methods are described that facilitate integrating ArF core patterning of floating gate structures in a flash memory device followed by KrF periphery gate patterning using a hard mask comprising a material such as amorphous carbon to facilitate core gate construction. The amorphous carbon hard mask can facilitate preparing such core gate structures while protecting periphery gate stacks such that the periphery stacks are ready for immediate KrF lithography upon completion of core gate formation without requiring additional resist deposition between core and periphery etches.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 16, 2008
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Marina V. Plat, Scott A. Bell
  • Publication number: 20080142873
    Abstract: A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
    Type: Application
    Filed: December 16, 2006
    Publication date: June 19, 2008
    Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.
    Inventors: Angela T. Hui, Mark S. Chang, Kuo-Tung Chang, Scott A. Bell
  • Patent number: 7368225
    Abstract: There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: May 6, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Scott A. Bell, Todd P. Lukanc, Marina V. Plat, Uzodinma Okoroanyanwu, Hung-Eil Kim
  • Patent number: 7361588
    Abstract: A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: April 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Phillip L. Jones, Mark S. Chang, Scott A. Bell
  • Publication number: 20080023751
    Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.
    Inventors: Amol Ramesh Joshi, Harpreet Sachar, YouSeok Suh, Shenqing Fang, Chih-Yuh Yang, Lovejeet Singh, David H. Matsumoto, Hidehiko Shiraiwa, Kuo-Tung Chang, Scott A. Bell, Allison Holbrook, Satoshi Torii
  • Patent number: 7285499
    Abstract: A method includes forming a group of first structures on a semiconductor device and forming spacers adjacent side surfaces of each of the first structures to form a group of second structures. The method further includes using the group of second structures to form at least one sub-lithographic opening in a material layer located below the group of second structures.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: October 23, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott A. Bell, Phillip Lawrence Jones, Angela T. Hui
  • Publication number: 20070222604
    Abstract: An RFID bridge antenna is positioned between a tag antenna associated with a tag and a reader antenna associated with a reader. The bridge includes at least two RF antenna elements spaced apart from one another and coupled together by an electrical conductor. The first RF antenna element is located proximate to the tag antenna and the second RF antenna element is located proximate to the reader antenna. An electromagnetic carrier signal transmitted by the reader antenna is received by one of the RF antenna element and retransmitted to the tag antenna by the other RF antenna element, increasing the distance over which the tag can communicate with the reader. Where the tag is attached to a packaged object, the RFID bridge antenna may be included in the package to allow wireless data communication between the tag and a reader. The reader may also be located external to the package.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 27, 2007
    Inventors: William Phipps, Alberto Rodriguez, Scott Bell, Heiko Rommelmann
  • Publication number: 20070222606
    Abstract: An RFID bridge antenna is positioned between a tag antenna associated with a tag and a reader antenna associated with a reader. The bridge includes at least two RF antenna elements spaced apart from one another and coupled together by an electrical conductor. The first RF antenna element is located proximate to the tag antenna and the second RF antenna element is located proximate to the reader antenna. An electromagnetic carrier signal transmitted by the reader antenna is received by one of the RF antenna element and retransmitted to the tag antenna by the other RF antenna element, increasing the distance over which the tag can communicate with the reader. Where the tag is attached to a packaged object, the RFID bridge antenna may be included in the package to allow wireless data communication between the tag and a reader. The reader may also be located external to the package.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 27, 2007
    Inventors: William Phipps, Alberto Rodriguez, Scott Bell, Heiko Rommelmann
  • Patent number: 7268066
    Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: September 11, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas J. Bonser, Marina V. Plat, Chih Yuh Yang, Scott A. Bell, Srikanteswara Dakshina-Murthy, Philip A. Fisher, Christopher F. Lyons
  • Publication number: 20070146138
    Abstract: An interface antenna is positioned between a tag antenna associated with a tag and a reader antenna associated with a reader. The interface antenna receives an electromagnetic carrier signal transmitted by the reader antenna and causes an increase in intensity of the electromagnetic carrier signal at the location of the tag antenna, thereby increasing the distance over which the tag can communicate with the reader. Where the tag is attached to a packaged object, the interface antenna may be included in the package to allow wireless data communication between the tag and a reader external to the package. For example, the interface antenna may be attached to a label on the package. At least a portion of the interface antenna may be formed from a conductive ink applied to the label and/or the container. The object may be a module, also known as a customer replaceable unit (CRU), and the tag may be configured as a customer replaceable unit monitor (CRUM).
    Type: Application
    Filed: December 22, 2005
    Publication date: June 28, 2007
    Inventors: Will Phipps, Alberto Rodriguez, Scott Bell, Heiko Rommelmann, Steven Hart
  • Publication number: 20070072437
    Abstract: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 29, 2007
    Inventors: Michael Brennan, Scott Bell
  • Publication number: 20070058991
    Abstract: An adapter suitable for installation in a machine in place of a customer replaceable unit monitor having a first interface format is described herein. Upon installation of the adapter in the machine, the adapter enables data communication between the machine and a customer replaceable unit monitor having a second interface format that is different than the first interface format. The first and second interface formats may include one or more of: configuration of an electrical interface of the customer replaceable unit monitor, configuration of a mechanical interface of the customer replaceable unit monitor, and configuration of data input to and output from the customer replaceable unit monitor. The adapter may be attached to a module before the module is installed in the machine to simplify installation of the adapter.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 15, 2007
    Inventors: Heiko Rommelmann, Jerry Money, Scott Bell, Alberto Rodriguez
  • Patent number: 7122455
    Abstract: For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: October 17, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Marina V. Plat, Srikanteswara Dakshina-Murthy, Scott A. Bell, Cyrus E. Tabery
  • Patent number: D541622
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: May 1, 2007
    Assignee: Hadrian Manufacturing Inc.
    Inventors: Jeffrey Scott Bell, Allan Patrick Smith, Gary Phillip Greenway
  • Patent number: D546971
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: July 17, 2007
    Assignee: Hadrian Manufacturing Inc.
    Inventors: Jeffrey Scott Bell, Allan Patrick Smith, Gary Phillip Greenway
  • Patent number: D562118
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: February 19, 2008
    Inventors: Jeffrey Scott Bell, Allan Patrick Smith, Gary Phillip Greenway